Patents by Inventor Brent A. Anderson

Brent A. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VERTICAL TRANSISTOR CONTACT FOR A MEMORY CELL WITH INCREASED DENSITY
    Publication number: 20200006353
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A second doped region is formed in portions of the first doped region in which portions the first doped region extends below the second doped region. A gate is formed alongside portions of a first fin. Portions of the second doped region and portions of the first doped region extending below the second doped region are removed. Portions of the gate are removed. A metal is deposited in the removed portion of the gate, the removed portion of second doped region, and the first doped region extending below the second doped region to create the contact.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • VERTICAL TRANSISTOR CONTACT FOR CROSS-COUPLING IN A MEMORY CELL
    Publication number: 20200006552
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A first fin is formed over the first doped region. A gate is formed alongside portions of the first fin. A void is created by removing the first fin to expose a portion of the first doped region. A metal is deposited in the void to create the contact.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR STRUCTURE WITH SELF-ALIGNED TOP JUNCTION THROUGH EARLY TOP SOURCE/DRAIN EPITAXY
    Publication number: 20190393341
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • REDUCED STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE FOOT PRINT THROUGH CONTROLLED BOTTOM SOURCE/DRAIN PLACEMENT
    Publication number: 20190378767
    Abstract: A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Ruqiang Bao, Brent A. Anderson, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan
  • Integrating a junction field effect transistor into a vertical field effect transistor
    Patent number: 10504889
    Abstract: Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang
  • Vertical field effect transistor with self-aligned contacts
    Patent number: 10497798
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Methods of forming merged source/drain regions on integrated circuit products
    Patent number: 10475904
    Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
  • INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET
    Publication number: 20190326179
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Brent A. Anderson, Edward J. Nowak
  • VERTICAL TRANSPORT DEVICES WITH GREATER DENSITY THROUGH MODIFIED WELL SHAPES
    Publication number: 20190319032
    Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.
    Type: Application
    Filed: April 17, 2018
    Publication date: October 17, 2019
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS
    Publication number: 20190318965
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Brent A. Anderson, Edward J. Nowak
  • BEOL self-aligned interconnect structure
    Patent number: 10431494
    Abstract: An interconnect structure is provided that includes an interconnect level that contains an interconnect dielectric material layer having a first electrically conductive via feature, an electrically conductive line feature, and a second electrically conductive via feature embedded in the interconnect dielectric material layer, wherein the first and second via features are self-aligned perpendicularly to, and along the direction of, the electrically conductive line feature.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Brent A. Anderson
  • Two Step Fin Etch and Reveal for VTFETs and High Breakdown LDVTFETs
    Publication number: 20190296142
    Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 26, 2019
    Inventors: Mona Ebrish, Xuefeng Liu, Brent Anderson, Huiming Bu, Junli Wang
  • Integrating a planar field effect transistor (FET) with a vertical FET
    Patent number: 10424516
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • VERTICAL TRANSPORT STATIC RANDOM-ACCESS MEMORY CELLS WITH TRANSISTORS OF ACTIVE REGIONS ARRANGED IN LINEAR ROWS
    Publication number: 20190287957
    Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
    Patent number: 10418462
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • VERTICAL FIELD EFFECT TRANSISTORS
    Publication number: 20190267291
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventors: Brent A. ANDERSON, Edward J. NOWAK
  • Variable gate lengths for vertical transistors
    Patent number: 10395992
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Vertical transistor fabrication and devices
    Patent number: 10388757
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS
    Publication number: 20190252267
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Squeegee with seal flap
    Patent number: 10376121
    Abstract: The present invention relates generally to a surface cleaning squeegee assembly and more specifically to a squeegee assembly mounted on a scrubber-dryer floor cleaning machine. The squeegee assembly includes a front squeegee having a number of spaced channels along a lower edge covered by seal flaps, and a rear squeegee having no channels. The front and rear squeegees define a vacuum chamber between them. Air, dirty water and surfactant are vacuumed into the vacuum chamber through the front squeegee channels for ultimate disposal. When the scrubber-dryer surface cleaning machine traverses over an uneven surface, the seal flaps close the channels to limit or eliminate any vacuum loss to the vacuum chamber.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 13, 2019
    Assignee: Midwest Rubber Service & Supply Company
    Inventors: Brent Anderson, A.L.F. Meijdam