Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Abstract: A laser structure including a Si or Ge substrate, a III-V buffer layer formed on the substrate, a light emitting diode (LED) formed on the buffer layer configured to produce visible light, a lens disposed on the LED to focus light from the LED, a photonic crystal layer formed on the LED to receive the light focused by the lens, and a monolayer semiconductor nanocavity laser formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED. The LED and the laser are formed monolithically and the LED acts as an optical pump for the laser.

Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Abstract: Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.

Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Abstract: According to an embodiment of the present invention, a method of producing a computing device includes providing a semiconductor substrate, and patterning a mask on the semiconductor substrate, the mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate. The method includes implanting the first portion of the semiconductor substrate with a dopant. The method includes annealing the first portion of the semiconductor substrate to form an annealed doped region, while maintaining the second portion of the semiconductor substrate as an unannealed portion.

Abstract: According to an embodiment of the present invention, a method of producing a computing device includes providing a semiconductor substrate, and patterning a mask on the semiconductor substrate, the mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate. The method includes implanting the first portion of the semiconductor substrate with a dopant. The method includes annealing the first portion of the semiconductor substrate to form an annealed doped region, while maintaining the second portion of the semiconductor substrate as an unannealed portion.

Abstract: Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.

Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.

Abstract: Aspects of the present disclosure include a semiconductor structure comprising a gate layer with an associated gate dielectric thereon, and a region comprising at least one fin structure in contact with the gate layer, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials is a Zn based material.

Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: Techniques for high throughput electron channeling contrast imaging (ECCI) by varying electron beam energy are provided. In one aspect, a method for ECCI of a crystalline wafer includes: placing the crystalline wafer under an electron microscope having an angle of less than 90° relative to a surface of the crystalline wafer; generating an electron beam, by the electron microscope, incident on the crystalline wafer; varying an accelerating voltage of the electron microscope to access a channeling condition of the crystalline wafer; and obtaining an image of the crystalline wafer. A system for ECCI is also provided.

Abstract: In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.

Abstract: Techniques for high throughput electron channeling contrast imaging (ECCI) by varying electron beam energy are provided. In one aspect, a method for ECCI of a crystalline wafer includes: placing the crystalline wafer under an electron microscope having an angle of less than 90° relative to a surface of the crystalline wafer; generating an electron beam, by the electron microscope, incident on the crystalline wafer; varying an accelerating voltage of the electron microscope to access a channeling condition of the crystalline wafer; and obtaining an image of the crystalline wafer. A system for ECCI is also provided.

Abstract: Aspects of the present disclosure include a semiconductor structure comprising a gate layer with an associated gate dielectric thereon, and a region comprising at least one fin structure in contact with the gate layer, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials is a Zn based material.

Abstract: A laser structure including a Si or Ge substrate, a III-V buffer layer formed on the substrate, a light emitting diode (LED) formed on the buffer layer configured to produce visible light, a lens disposed on the LED to focus light from the LED, a photonic crystal layer formed on the LED to receive the light focused by the lens, and a monolayer semiconductor nanocavity laser formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED. The LED and the laser are formed monolithically and the LED acts as an optical pump for the laser.

Abstract: A method for forming a pumped laser structure includes forming a III-V buffer layer on a substrate including one of Si or Ge; forming a light emitting diode (LED) on the buffer layer configured to produce a threshold pump power; forming a photonic crystal layer on the LED and depositing a monolayer semiconductor nanocavity laser on the photonic crystal layer for receiving light through the photonic crystal layer from the LED with an optical pump power greater than the threshold pump power, wherein the LED and the laser are formed monolithically and the LED functions as an optical pump for the laser.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.