Abstract: A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release for manufacturing, a binding code may be established between the host and the non-volatile memory. In some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.

Abstract: Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window.

Abstract: A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol, As a result, prior to release for manufacturing, a binding code may k established between the host and the non-volatile memory, In some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.

Abstract: A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release for manufacturing, a binding code may be established between the host and the non-volatile memory. In some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.

Abstract: A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release for manufacturing, a binding code may be established between the host and the non-volatile memory. In some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.

Abstract: A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release for manufacturing, a binding code may be established between the host and the non-volatile memory. In some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.

Abstract: Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window.

Abstract: Methods and systems are provided that may include a nonvolatile memory to implement a virtual random access memory space.

Abstract: Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window.

Abstract: Methods and systems are provided that may include a controller comprising an access element and a command interface. Access element may provide access to a physical nonvolatile memory device. Physical nonvolatile memory device may have a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device. A command interface may modify access to the physical nonvolatile memory device by issuing a command through at least one write overlay window of a memory partition to change the default setting to write to the physical nonvolatile memory. The at least one write overlay window may be logically separate from at least one read overlay window of the memory partition.

Abstract: Embodiments include but are not limited to apparatuses and systems including a memory array including a plurality of non-volatile memory cells, and a control signal output pin operatively coupled to the memory array. The control signal output pin may be configured to provide a control signal indicative of the memory interface control flow including, for example, an availability of the memory array for reading or writing. Other embodiments may be described and claimed.

Abstract: A memory operating in an execute-in-place (XIP) type mode returns a default instruction when an nV memory core is not ready for access. The default instruction may be selected to provide a system stall when executed within a corresponding processor.

Abstract: The time used in manufacturing an electronic device can be reduced by reducing the amount of time taken to store code on non-volatile memories. In one embodiment, storing compressed code to a non-volatile memory can reduce the manufacturing time of an electronic device. The code stored on the non-volatile memory can be decompressed by a controller in the electronic device and loaded on the non-volatile memory for execution by the electronic device.

Abstract: An authenticatable envelope is utilized to allow for the secure and quasi-atomic delivery and execution of an ordered list of externally specified non-volatile memory write commands. In at least some embodiments, an external provider generates an authenticatable envelope that includes write commands and data that is used by a local platform of a non-volatile memory device to generate non-volatile memory write data in response to the write commands.

Abstract: The time used in manufacturing an electronic device can be reduced by reducing the amount of time taken to store code on non-volatile memories. In one embodiment, storing compressed code to a non-volatile memory can reduce the manufacturing time of an electronic device. The code stored on the non-volatile memory can be decompressed by a controller in the electronic device and loaded on the non-volatile memory for execution by the electronic device.

Abstract: A memory operating in an execute-in-place (XIP) type mode returns a default instruction when an nV memory core is not ready for access. The default instruction may be selected to provide a system stall when executed within a corresponding processor.

Abstract: An apparatus, system, and method for a data invalid signal for non-deterministic latency in memory are described. The apparatus may include a memory to determine that data to be buffered for a data burst cannot be guaranteed in time to satisfy a deterministic latency parameter. The memory may provide an indication that the data cannot be guaranteed. Other embodiments are described and claimed.