Patents by Inventor Brent Alan Fairbanks

Brent Alan Fairbanks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030182645
    Abstract: A technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic design file. A set of design rules expressing permitted and prohibited structural and functional logic device relationships is provided as a portion of a logic design simulation system capable of synthesizing the initial design into a simulated network list. The initial design is checked against the various design rules incorporated into the set, and any violation of the design rules by the initial logic design is visibly displayed to the user. In one mode of operation, a list of user selectable optional rules is visibly displayed. A hierarchy of levels of design compliance is also displayed for user selection. For some design rules, a comparison can be made with the synthesized version of the initial logic design in order to spot design rule violations introduced by the synthesis process.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 25, 2003
    Applicant: Altera Corporation
    Inventor: Brent Alan Fairbanks
  • Patent number: 6601221
    Abstract: A technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic design file. A set of design rules expressing permitted and prohibited structural and functional logic device relationships is provided as a portion of a logic design simulation system capable of synthesizing the initial design into a simulated network list. The initial design is checked against the various design rules incorporated into the set, and any violation of the design rules by the initial logic design is visibly displayed to the user. In one mode of operation, a list of user selectable optional rules is visibly displayed. A hierarchy of levels of design compliance is also displayed for user selection. For some design rules, a comparison can be made with the synthesized version of the initial logic design in order to spot design rule violations introduced by the synthesis process.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: July 29, 2003
    Assignee: Altera Corporation
    Inventor: Brent Alan Fairbanks
  • Patent number: 6182020
    Abstract: A technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic design file. A set of design rules expressing permitted and prohibited structural and functional logic device relationships is provided as a portion of a logic design simulation system capable of synthesizing the initial design into a simulated network list. The initial design is checked against the various design rules incorporated into the set, and any violation of the design rules by the initial logic design is visibly displayed to the user. In one mode of operation, a list of user selectable optional rules is visibly displayed. A hierarchy of levels of design compliance is also displayed for user selection. For some design rules, a comparison can be made with the synthesized version of the initial logic design in order to spot design rule violations introduced by the synthesis process.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: January 30, 2001
    Assignee: Altera Corporation
    Inventor: Brent Alan Fairbanks