Patents by Inventor Brent C. Beardsley
Brent C. Beardsley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9542330Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks.Type: GrantFiled: March 31, 2016Date of Patent: January 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 9323694Abstract: Storage tracks from at least one server are destaged from the write cache rank when it is determined that the at least one server is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one server is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.Type: GrantFiled: June 1, 2015Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 9317447Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.Type: GrantFiled: June 1, 2015Date of Patent: April 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 9069683Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.Type: GrantFiled: January 17, 2014Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 9063863Abstract: Storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. The storage tracks are refrained from being destaged from the write cache if the at least one host is not idle. Each rank is monitored for write operations from the at least one host, and a determination is made if the at least one host is idle with respect to each respective rank based on monitoring each rank for write operations from the at least one host such that the at least one host may be determined to be idle with respect to a first rank and not idle with respect to a second rank.Type: GrantFiled: February 6, 2014Date of Patent: June 23, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8996813Abstract: Destaging storage tracks from each rank that includes a greater than a predetermined percentage of a predetermined amount of storage space with respect to a current amount of storage space allocated to each rank until the current amount of storage space used by each respective rank is equal to the predetermined percentage of the predetermined amount of storage space. The destage storage tracks are declined from being destaged from each rank that includes less than or equal to the predetermined percentage of the predetermined amount of storage space rank.Type: GrantFiled: February 6, 2014Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8661202Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. Also provided are physical computer storage mediums including a computer program product for performing the above method.Type: GrantFiled: December 10, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8661201Abstract: A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank. Also provided are physical computer storage mediums including code that, when executed by a processor, cause the processor to perform the above method.Type: GrantFiled: December 10, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8656109Abstract: A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.Type: GrantFiled: December 10, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8639888Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.Type: GrantFiled: December 10, 2010Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8595433Abstract: A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank.Type: GrantFiled: June 11, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8589624Abstract: A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle.Type: GrantFiled: June 11, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8589623Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.Type: GrantFiled: June 11, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8566535Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.Type: GrantFiled: June 11, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
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Patent number: 8566518Abstract: Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.Type: GrantFiled: May 23, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
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Patent number: 8549220Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each of a plurality of strides in a modified cache, wherein the multi-update bit is adapted to indicate a corresponding stride is part of at least one track in a working set that refers to a group of frequently updated tracks. The plurality of strides are scanned based on a schedule to identify tracks for destaging. An operation to destage is performed on a selected track identified during the scanning, if the multi-update bit of a selected stride on the selected track is set to indicate the selected track is part of the working set and if the NVS is about 90% full or greater.Type: GrantFiled: September 14, 2012Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
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Patent number: 8443141Abstract: Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.Type: GrantFiled: September 29, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
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Patent number: 8332589Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each stride in a modified cache. The multi-update bit is adapted to indicate at least one track in a working set. A schedule of destage scans is configured based on a plurality of levels of urgency. A destage operation is performed based on at least one of a number of strides examined by the destage scans, whether the multi-update bit is set, and whether an emergency level of the plurality of levels of urgency is active.Type: GrantFiled: September 29, 2010Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
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Patent number: 7676616Abstract: A method, apparatus and program storage device for providing asynchronous status messaging in a data storage system Asynchronous events are returned from a target to an initiator in response to a Read Message from the initiator. The return status message may or may not be associated with a previously given command or Logical Unit (LUN).Type: GrantFiled: September 7, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Minh-Ngoc Le Huynh, William F. Micka, Satish Chandra Penmetsa, Richard A. Schaeffer, Kaukab Uddin
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Patent number: 7290086Abstract: A method, apparatus and program storage device for providing asynchronous status messaging in a data storage system Asynchronous events are returned from a target to an initiator in response to a Read Message from the initiator. The return status message may or may not be associated with a previously given command or Logical Unit (LUN).Type: GrantFiled: May 28, 2003Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Brent C. Beardsley, Minh-Ngoc Le Huynh, William F. Micka, Satish Chandra Penmetsa, Richard A. Schaeffer, Kaukab Uddin