Patents by Inventor Brent Carl Byron

Brent Carl Byron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147669
    Abstract: Various embodiments provide for incremental power throttling on a memory system, such as a memory sub-system. In particular, for some embodiments, incremental power throttling is implemented on a memory system using one or more power credit allocations and memory operation progress tracking.
    Type: Application
    Filed: November 5, 2024
    Publication date: May 8, 2025
    Inventors: Brent Carl Byron, Suresh Rajgopal, Shakeel Bukhari, Jeonghun Kim
  • Publication number: 20250053329
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to receive information from a host about invalidated memory addresses. The controller receives, from a host, data identifying a set of storage locations associated with invalidated data stored in a set of memory components and, in response to receiving the data, performs staging activity for the invalidated data stored in the set of storage locations. The controller receives, from the host, a trim command for one or more storage locations in the set of storage locations and performs trim operations for the one or more storage locations for which the staging activity has already been performed.
    Type: Application
    Filed: July 29, 2024
    Publication date: February 13, 2025
    Inventors: Sampath Ratnam, Daniel J. Hubbard, Kevin R. Brandt, David Ebsen, Brent Carl Byron
  • Publication number: 20250036303
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to control storage on the memory sub-system based on endurance of memory components. The controller groups the set of memory components into a plurality of categories representing different endurance levels of the set of memory components and communicates, to a host, information about the plurality of categories. The controller receives, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and an individual category associated with the individual memory component.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Inventors: Kevin R. Brandt, Sampath Ratnam, David Ebsen, Brent Carl Byron, Daniel J. Hubbard
  • Publication number: 20250028600
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to configure data storage policies on the memory sub-system. The controller receives, from a host, a data storage policy instruction, the data storage policy instruction defining how data is stored on a set of memory components. The controller updates configuration information for the memory sub-system based on the data storage policy instruction received from the host and controls storage of data to the set of memory components based on the updated configuration information.
    Type: Application
    Filed: July 19, 2024
    Publication date: January 23, 2025
    Inventors: Brent Carl Byron, Kevin R. Brandt, Sampath Ratnam, David Ebsen, Daniel J. Hubbard
  • Publication number: 20250028483
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to deallocate data prior to folding operations. The controller generates an instruction to fold data stored in an individual portion of the set of memory components. The controller, prior to executing the instruction to fold the data stored in the individual portion of the set of memory components, transmits a communication to a host indicative of the instruction to fold the data stored in the individual portion. The controller conditions execution of the instruction to fold the data stored in the individual portion of the set of memory components based on transmission of the communication to the host.
    Type: Application
    Filed: July 17, 2024
    Publication date: January 23, 2025
    Inventors: Daniel J. Hubbard, Kevin R. Brandt, David Ebsen, Sampath Ratnam, Brent Carl Byron
  • Publication number: 20250028479
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to inform a host about write amplification penalty for host invalidations. The controller generates a virtual memory group comprising a portion of a memory component of a set of memory components. The controller computes a write amplification penalty associated with invalidating data associated with the virtual memory group. The controller communicates, to a host, information about the write amplification penalty associated with invalidating data associated with the virtual memory group. The controller receives, from the host, a request to invalidate data associated with the virtual memory group, the request being generated by the host based on the write amplification penalty.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 23, 2025
    Inventors: David Ebsen, Daniel J. Hubbard, Kevin R. Brandt, Sampath Ratnam, Brent Carl Byron
  • Patent number: 11550737
    Abstract: Various embodiments described herein provide for operation of a memory sub-system based on a profile (also referred to herein as an operational profile) that causes the memory sub-system to have a specific set of operational characteristics. Additionally, some embodiments can provide dynamic switching between profiles based on a set of conditions being satisfied, such as current time of day or detection of a particular data input/out (I/O) pattern with respect to the memory sub-system.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Brent Carl Byron
  • Publication number: 20210089229
    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device detects a triggering condition for updating one or more media settings of a memory component of the plurality of memory components, and responsively instructs the memory component to load, from data storage on the memory component, a set of one or more media-setting values that correspond to the one or more media settings of the memory component.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Douglas Eugene Majerus, Scott Anthony Stoller, Brent Carl Byron
  • Publication number: 20210034553
    Abstract: Various embodiments described herein provide for operation of a memory sub-system based on a profile (also referred to herein as an operational profile) that causes the memory sub-system to have a specific set of operational characteristics. Additionally, some embodiments can provide dynamic switching between profiles based on a set of conditions being satisfied, such as current time of day or detection of a particular data input/out (I/O) pattern with respect to the memory sub-system.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventor: Brent Carl Byron