Patents by Inventor Brent Carlton
Brent Carlton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145750Abstract: Provided is a microbial fuel cell including a cathode and an anode, wherein the cathode includes a waterproof gas diffusion layer including a siloxane and a catalyst layer including a binder, wherein a surface of the gas diffusion layer opposite the catalyst layer contacts air, and the anode includes electrogenic bacteria. Also provided is a method for making a microbial fuel cell, including fabricating a cathode, wherein fabricating includes disposing a siloxane solution onto a surface of a substrate, wherein the siloxane solution includes a siloxane and a solvent, drying the siloxane solution to form a waterproof gas diffusion layer, and placing the gas diffusion layer on a catalyst layer including a binder, and facing an anode with the cathode whereby the gas diffusion layer faces away from the anode and contacts air.Type: ApplicationFiled: May 25, 2023Publication date: May 2, 2024Applicant: MICRORGANIC TECHNOLOGIES, INC.Inventors: Brent A. Solina, Alex Carlton
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Publication number: 20240113725Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Brent Carlton
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Publication number: 20240097693Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Somnath KUNDU, Amy L. WHITCOMBE, Stefano PELLERANO, Peter SAGAZIO, Brent CARLTON
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Publication number: 20240045723Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.Type: ApplicationFiled: September 29, 2023Publication date: February 8, 2024Inventors: Deepak Dasalukunte, Richard Dorrance, Renzhi Liu, Henchen Wang, Brent Carlton
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Publication number: 20240020093Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.Type: ApplicationFiled: September 29, 2023Publication date: January 18, 2024Inventors: Richard Dorrance, Deepak Dasalukunte, Renzhi Liu, Hechen Wang, Brent Carlton
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Publication number: 20230291433Abstract: A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.Type: ApplicationFiled: June 25, 2021Publication date: September 14, 2023Inventors: Ofer Benjamin, Eli Borokhovich, Brent Carlton, Ofir Degani, Ronen Kronfeld, Stefano Pellerano, Mustafijur Rahman, Ehud Reshef, Sarit Zur
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Publication number: 20230289066Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.Type: ApplicationFiled: March 22, 2023Publication date: September 14, 2023Inventors: Renzhi Liu, Hechen Wang, Richard Dorrance, Deepak Dasalukunte, Brent Carlton
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Publication number: 20230251943Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.Type: ApplicationFiled: April 11, 2023Publication date: August 10, 2023Inventors: Richard Dorrance, Renzhi Liu, Hechen Wang, Deepak Dasalukunte, Brent Carlton
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Publication number: 20230229504Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.Type: ApplicationFiled: September 30, 2022Publication date: July 20, 2023Inventors: Renzhi Liu, Hechen Wang, Richard Dorrance, Deepak Dasalukunte, Brent Carlton
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Publication number: 20230018398Abstract: A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.Type: ApplicationFiled: June 8, 2021Publication date: January 19, 2023Applicant: Intel CorporationInventors: Amy Whitcombe, Brent Carlton
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Patent number: 11528066Abstract: Methods, apparatus, and computer-readable media are described to use multi-finger beamforming for multimeter wave communications. A base station associates with first and second user equipment. Weight sum rates are determined for the user equipment. Transmissions are scheduled to the user equipment based on the weight sum rates. Data is encoded for the first user equipment and transmitted based on the schedule. Data is encoded for the second user equipment and transmitted based on the schedule. The transmissions are multiplexed in the power domain.Type: GrantFiled: July 12, 2018Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Oner Orhan, Ehsan Aryafar, Brent Carlton, Nageen Himayat, Christopher Hull, Navid Naderializadeh, Hosein Nikopour, Stefano Pellerano, Mustafijur Rahman, Shilpa Talwar, Jing Zhu
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Publication number: 20220393688Abstract: An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Applicant: Intel CorporationInventors: Somnath Kundu, Hao Luo, Brent Carlton
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Publication number: 20220229495Abstract: Techniques for radiofrequency (RF) touch and gesture recognition are disclosed. In the illustrative embodiment, RF transmitters and receivers are connected to data lines and gate lines of a display. RF signals sent on one data or gate line may be scattered to a different data or gate line based on the presence of a nearby object, such as a finger. The amount of scattering on different data or gate lines can be used to determine a location of one or more objects.Type: ApplicationFiled: April 1, 2022Publication date: July 21, 2022Applicant: Intel CorporationInventors: Hao Luo, Somnath Kundu, Brent Carlton, Zhen Zhou
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Publication number: 20220085822Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.Type: ApplicationFiled: September 17, 2020Publication date: March 17, 2022Applicant: Intel CorporationInventors: Somnath Kundu, Abhishek Agrawal, Brent Carlton
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Patent number: 11277143Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.Type: GrantFiled: September 17, 2020Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Somnath Kundu, Abhishek Agrawal, Brent Carlton
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Patent number: 11205995Abstract: An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.Type: GrantFiled: March 27, 2020Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Brent Carlton, Hao Luo, Somnath Kundu
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Publication number: 20210305939Abstract: An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Brent Carlton, Hao Luo, Somnath Kundu
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Patent number: 11044671Abstract: A communication device can include a receiver frontend and a wake-up receiver (WUR) frontend. The receiver frontend can have a radio frequency (RF) interface configured to couple to an antenna and a baseband interface configured to couple to a baseband component. The WUR frontend can be selectively coupled to the receiver frontend (e.g. between the RF interface and the baseband interface). The WUR frontend may monitor a communication channel and control the receiver frontend to adjust its operating mode (e.g. waking the receiver frontend from a sleep mode) based on the monitoring. The WUR frontend may have a lower power consumption than the receiver frontend. The WUR frontend and the receiver frontend may share the same impedance matching network and/or the RF interface.Type: GrantFiled: March 29, 2019Date of Patent: June 22, 2021Assignee: Intel CorporationInventors: Renzhi Liu, Asma Beevi Kuriparambil Thekkumpate, Brent Carlton
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Publication number: 20210028840Abstract: Methods, apparatus, and computer-readable media are described to use multi-finger beamforming for multimeter wave communications. A base station associates with first and second user equipment. Weight sum rates are determined for the user equipment. Transmissions are scheduled to the user equipment based on the weight sum rates. Data is encoded for the first user equipment and transmitted based on the schedule. Data is encoded for the second user equipment and transmitted based on the schedule. The transmissions are multiplexed in the power domain.Type: ApplicationFiled: July 12, 2018Publication date: January 28, 2021Inventors: Oner Orhan, Ehsan Aryafar, Brent Carlton, Nageen Himayat, Christopher Hull, Navid Naderializadeh, Hosein Nikopour, Stefano Pellerano, Mustafijur Rahman, Shilpa Talwar, Jing Zhu
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Patent number: 10873360Abstract: Systems, methods, and circuitries are disclosed for performing self-interference cancellation in a transceiver. In one example, a self-interference cancellation system includes a cancellation signal circuitry, cancellation circuitry, down-conversion circuitry, and an LO derivation circuitry. The cancellation signal circuitry is configured to use a cancellation transmit (TX) local oscillator (LO) signal to up-convert a baseband transmit leakage replica signal to generate a cancellation signal. The cancellation circuitry is configured to combine the cancellation signal with a received signal to generate a corrected received signal. The down-conversion circuitry is configured to use a receive (RX) LO signal to down-convert the corrected received signal to generate a baseband received signal. The LO derivation circuitry is configured to derive the cancellation TX LO signal and the RX LO signal from a common LO signal.Type: GrantFiled: March 26, 2019Date of Patent: December 22, 2020Assignee: INTEL CORPORATIONInventors: Ritesh Bhat, Stefano Pellerano, Brent Carlton