Patents by Inventor Brent E. BUCHANAN

Brent E. BUCHANAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell having resistive and capacitive storage elements
    Patent number: 9911495
    Abstract: A technique including using an array of memory cells for data storage. A given cell of the memory cells includes a capacitive storage element and a resistive storage element that is coupled in series with the capacitive storage element. The technique includes accessing the given memory cell to write a value to the given memory cell or read a value stored in the memory cell. The accessing includes applying a time varying voltage to the memory cell.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 6, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent E. Buchanan
  • Resistive ratio-based memory cell
    Patent number: 9754666
    Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: September 5, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent E. Buchanan, Martin Foltin, Jeffrey A. Lucas, Clinton H. Parker
  • MEMORY CELL HAVING RESISTIVE AND CAPACITIVE STORAGE ELEMENTS
    Publication number: 20160351260
    Abstract: A technique including using an array of memory cells for data storage. A given cell of the memory cells includes a capacitive storage element and a resistive storage element that is coupled in series with the capacitive storage element. The technique includes accessing the given memory cell to write a value to the given memory cell or read a value stored in the memory cell. The accessing includes applying a time varying voltage to the memory cell.
    Type: Application
    Filed: January 31, 2014
    Publication date: December 1, 2016
    Inventor: Brent E. BUCHANAN
  • RESISTIVE RATIO-BASED MEMORY CELL
    Publication number: 20160336063
    Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.
    Type: Application
    Filed: January 31, 2014
    Publication date: November 17, 2016
    Inventors: Brent E. BUCHANAN, Martin FOLTIN, Jeffrey A. LUCAS, Clinton H. PARKER
  • ACCESSING A RESISTIVE STORAGE ELEMENT-BASED MEMORY CELL ARRAY
    Publication number: 20160336062
    Abstract: A technique includes reading a row of memory cells of a memory cell array, where each of the memory cells includes comprising a resistive storage element and is associated with a column line. The technique includes, in association with the reading, coupling the column lines to a ground connection.
    Type: Application
    Filed: January 31, 2014
    Publication date: November 17, 2016
    Inventor: Brent E. BUCHANAN