Abstract: A bridge circuit includes a microprocessor having a first I/O port which couples to a SCSI bus and a second I/O port which is coupled through transceivers to an EISA bus. Also, the bridge circuit includes an EISA interface controller, having control lines coupled to the EISA bus and the transceivers, which enable the microprocessor to request and use the EISA bus in time-shared fashion. In order to achieve a high speed of operation, the bridge circuit further includes a memory module, coupled via a private bus to the second I/O port of the microprocessor, which sends instructions on the private bus directly to the microprocessor, without generating any signals on the EISA bus. In addition, in order to prevent deadlocks on the private bus, the bridge circuit includes a deadlock prevention circuit which is coupled to the microprocessor and the private bus and the EISA interface controller.