Abstract: A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled “SLIME.” The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status.

Abstract: A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.

Abstract: A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

Abstract: A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.