Patents by Inventor Brent Gilgen

Brent Gilgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134741
    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee
  • Publication number: 20180019245
    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 18, 2018
    Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee
  • Patent number: 9812455
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: November 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Patent number: 9754946
    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee
  • Patent number: 9589962
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Publication number: 20160336325
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Publication number: 20150364414
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Patent number: 9171750
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: October 27, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Brent Gilgen
  • Publication number: 20150132934
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventor: Brent Gilgen
  • Patent number: 8957483
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Brent Gilgen
  • Publication number: 20130256811
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 3, 2013
    Inventor: Brent Gilgen
  • Patent number: 8470654
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Brent Gilgen
  • Patent number: 8450218
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Brent Gilgen
  • Publication number: 20120100726
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 26, 2012
    Inventors: Yunjun Ho, Brent Gilgen
  • Patent number: 8105956
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Brent Gilgen
  • Publication number: 20110204453
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Application
    Filed: February 23, 2010
    Publication date: August 25, 2011
    Inventor: Brent Gilgen
  • Publication number: 20110092061
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Inventors: Yunjun Ho, Brent Gilgen
  • Patent number: 7545009
    Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Yongjun Jeff Hu, Luan Tran, Brent Gilgen
  • Publication number: 20080019167
    Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
    Type: Application
    Filed: August 2, 2007
    Publication date: January 24, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Trung Doan, D. Durcan, Brent Gilgen
  • Patent number: 7115970
    Abstract: Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various embodiments of the method a bottom electrode adapted to act as an etch stop is formed, a substantially cone-shaped first plate of conductive material is formed having an interior and exterior surface and terminating at the bottom electrode, a layer of dielectric material is formed on at least a portion of the interior and exterior surface of the first plate and substantially conforming to the shape of the first plate, and a second plate of conductive material is formed over the layer of dielectric material. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brent Gilgen, Belford T. Coursey