Patents by Inventor Brent Gilgen
Brent Gilgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 10134741Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 18, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Methods Of Forming An Elevationally Extending Conductor Laterally Between A Pair Of Conductive Lines
Publication number: 20180019245Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: ApplicationFiled: July 18, 2017Publication date: January 18, 2018Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Patent number: 9812455Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.Type: GrantFiled: July 25, 2016Date of Patent: November 7, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
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Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 9754946Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 14, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Patent number: 9589962Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.Type: GrantFiled: June 17, 2014Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
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Publication number: 20160336325Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
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Publication number: 20150364414Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.Type: ApplicationFiled: June 17, 2014Publication date: December 17, 2015Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
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Patent number: 9171750Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: GrantFiled: January 22, 2015Date of Patent: October 27, 2015Assignee: Micron Technology, Inc.Inventor: Brent Gilgen
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Publication number: 20150132934Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Inventor: Brent Gilgen
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Patent number: 8957483Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: GrantFiled: June 5, 2013Date of Patent: February 17, 2015Assignee: Micron Technology, Inc.Inventor: Brent Gilgen
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Publication number: 20130256811Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: ApplicationFiled: June 5, 2013Publication date: October 3, 2013Inventor: Brent Gilgen
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Patent number: 8470654Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: GrantFiled: February 23, 2010Date of Patent: June 25, 2013Assignee: Micron Technology, Inc.Inventor: Brent Gilgen
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Patent number: 8450218Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: December 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Publication number: 20120100726Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: ApplicationFiled: December 28, 2011Publication date: April 26, 2012Inventors: Yunjun Ho, Brent Gilgen
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Patent number: 8105956Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: October 20, 2009Date of Patent: January 31, 2012Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Publication number: 20110204453Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Inventor: Brent Gilgen
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Publication number: 20110092061Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: ApplicationFiled: October 20, 2009Publication date: April 21, 2011Inventors: Yunjun Ho, Brent Gilgen
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Patent number: 7545009Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.Type: GrantFiled: March 4, 2005Date of Patent: June 9, 2009Assignee: Micron Technology, Inc.Inventors: Ravi Iyer, Yongjun Jeff Hu, Luan Tran, Brent Gilgen
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Publication number: 20080019167Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.Type: ApplicationFiled: August 2, 2007Publication date: January 24, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Trung Doan, D. Durcan, Brent Gilgen
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Patent number: 7115970Abstract: Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various embodiments of the method a bottom electrode adapted to act as an etch stop is formed, a substantially cone-shaped first plate of conductive material is formed having an interior and exterior surface and terminating at the bottom electrode, a layer of dielectric material is formed on at least a portion of the interior and exterior surface of the first plate and substantially conforming to the shape of the first plate, and a second plate of conductive material is formed over the layer of dielectric material. Other aspects and embodiments are provided herein.Type: GrantFiled: September 1, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Brent Gilgen, Belford T. Coursey