Abstract: The specification describes a process for making a plating mask (17), for use in printed wiring board fabrication, with greater precision and definition than has previously been possible. An insulative substrate (11) includes on one surface a thin metal film (13). The film is covered with a relatively thick first mask layer (16) which is selectively removed to expose portions of the metal film, which are in turn removed to expose portions of the insulative substrate (11). The exposed portions of the insulative substrate are covered with a relatively thick plating mask layer (17) which abuts against the first mask layer (16). The first mask layer is then removed, leaving the remaining plating mask layer as a patterned plating mask which is then used as a mask for deposited metal (19) which defines a printed circuit.

Abstract: In a hybrid integrated circuit encapsulation process, each lead array (14) is encompassed by an elongated C-shaped barrier member (17) which clamps onto the portions of the lead array adjacent the substrate (11); that is, opposite sides of a slot (18) in the barrier member grasp opposite sides of the leads. Thereafter, the uncured RTV silicone (15) is dispensed onto the substrate, flows over and encompasses chips (12) mounted on the surface of the substrate and is prevented from flowing along the leads (14) by the C-shaped members (17), each of which, due to its configuration, constitutes a barrier to fluid flow, either along the length of the various leads or over the top of the C-shaped member. In one embodiment, levers (19) may be integrated onto the C-shaped member opposite the substrate to aid in prying open the slot to permit the leads to be easily inserted into the C-shaped member.