Patents by Inventor Brent Keeth

Brent Keeth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313098
    Abstract: Methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. A memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. For example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. The first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). The dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin
  • Publication number: 20240288925
    Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.
    Type: Application
    Filed: May 7, 2024
    Publication date: August 29, 2024
    Inventor: Brent Keeth
  • Publication number: 20240256473
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Inventors: Brent Keeth, Frank F Ross, Richard C Murphy
  • Patent number: 12045500
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Brent Keeth
  • Publication number: 20240237363
    Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 11, 2024
    Inventors: James Brian Johnson, Brent Keeth, Ameen D. Akel, Kunal R. Parekh, Amy Rae Griffin, Eiichi Nakano
  • Publication number: 20240194287
    Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin
  • Publication number: 20240186274
    Abstract: Methods, systems, and devices for thermal distribution techniques in coupled semiconductor systems are described. A semiconductor system may be formed by coupling various semiconductor components with one another, and may also implement a semiconductor material to support a thermal path having a thermal conductivity that is relatively close to a thermal conductivity through the coupled semiconductor components of the semiconductor system. Such a semiconductor material may be located in regions of the semiconductor system that are otherwise unoccupied by functional (e.g., electrically operable) semiconductor components and may, in some examples, be electrically inoperable (e.g., may lack functional circuitry). For implementations in which functional semiconductor components are directly coupled (e.g., by fusion bonding or hybrid bonding techniques), the semiconductor material may also be directly coupled with at least one of the semiconductor components.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Inventors: Amy Rae Griffin, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, James Brian Johnson, Ameen D. Akel
  • Publication number: 20240176523
    Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).
    Type: Application
    Filed: November 21, 2023
    Publication date: May 30, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin, Ameen D. Akel
  • Patent number: 11989141
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Frank F Ross, Richard C Murphy
  • Patent number: 11983059
    Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Brent Keeth
  • Publication number: 20240134677
    Abstract: Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called “protected regions”). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.
    Type: Application
    Filed: August 17, 2023
    Publication date: April 25, 2024
    Inventors: Brent Keeth, Naveh Malihi
  • Publication number: 20240111673
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Inventors: Brent Keeth, Owen Fay, Chan H. Yoo, Roy E. Greeff, Matthew B. Leslie
  • Publication number: 20240096852
    Abstract: Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventor: Brent Keeth
  • Publication number: 20240088084
    Abstract: An interface shim layer for a tightly-coupled random access memory device is disclosed. The interface shim layer redirects and coalesces integrated channels and connections between a stacked plurality of memory die and an application specific integrated circuit and directly connects to the memory die and to the application specific integrated circuit. A passive version of the interface shim layer incorporates a plurality of routing layers to facilitate routing of signals to and from the stacked plurality of memory die and the application specific integrated circuit. An active version of the interface shim layer incorporates separate physical interfaces for both the stacked plurality of memory die and the application specific integrated circuit to facilitate routing. The active version of the interface shim layer may further incorporate memory controller functions, built-in self-test circuits, among other capabilities that are migratable into the active interface shim layer.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Ameen D. Akel, Brent Keeth
  • Patent number: 11928025
    Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, Brent Keeth
  • Publication number: 20240070069
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
    Type: Application
    Filed: June 28, 2023
    Publication date: February 29, 2024
    Inventors: Brent Keeth, Owen Fay, Chan H. Yoo, Roy E. Greeff, Matthew B. Leslie
  • Publication number: 20240071556
    Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: James Brian Johnson, Kunal R. Parekh, Brent Keeth, Eiichi Nakano, Amy Rae Griffin
  • Patent number: 11893245
    Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 11887969
    Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: January 30, 2024
    Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
  • Patent number: 11868253
    Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 9, 2024
    Inventors: Brent Keeth, Owen Fay, Chan H. Yoo, Roy E. Greeff, Matthew B. Leslie