Patents by Inventor Brent M. Roberts

Brent M. Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9999129
    Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Mihir K. Roy, Brent M. Roberts
  • Patent number: 8659171
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 25, 2014
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan
  • Publication number: 20130141859
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan
  • Patent number: 8440506
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan
  • Patent number: 8389337
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan
  • Patent number: 8381393
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include attaching a patch to an interposer, forming at least one interconnect structure above and on a top surface of the interposer; and attaching a flex connector to the at least one interconnect structure.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
  • Publication number: 20120279059
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 8, 2012
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan
  • Patent number: 8278752
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
  • Publication number: 20110157808
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include attaching a patch to an interposer, forming at least one interconnect structure above and on a top surface of the interposer; and attaching a flex connector to the at least one interconnect structure.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
  • Publication number: 20110156276
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srninivasan
  • Publication number: 20110147913
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233,234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
  • Publication number: 20110108947
    Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Inventors: John S. Guzek, Mihir K. Roy, Brent M. Roberts
  • Patent number: 7629680
    Abstract: In some embodiments, direct power delivery into an electronic package is presented. In this regard, a substrate is introduced having a conductive substrate core designed to physically connect with a power cable. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Sriram Srinivasan