Patents by Inventor Brent M. Sherman

Brent M. Sherman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10484186
    Abstract: A method, computing system, and computer-readable medium comprising instructions to establish a chain of trust for components of a computing environment. A respective public/private key pair is generated using a multivariate quadratic function F for each component of the computing environment. In response to a challenge from a verifier, a current prover component sends a response that the verifier uses to determine whether to trust the current prover component. The response may include a first commitment value and a second commitment value, which are determined for the current prover component using a public key of a previous prover component. At least one of the first and second commitment values can be determined using a polar function G, which is a polar form of the multivariate quadratic function F.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventor: Brent M. Sherman
  • Patent number: 10367641
    Abstract: Embodiments of a system and method for creating a chain of trust are generally described herein. A method may include generating a private secret value, determining a public test value using the private secret value, sending, from a first device in a trusted environment with a second device and a third device, the public test value to the second device, receiving, at the first device outside the trusted environment, a challenge from the third device, determining a verification to the challenge using the private secret value, sending, from the first device outside the trusted environment, the verification to the second device, and receiving, at the first device outside the trusted environment, confirmation from the third device that the verification was successfully verified by the second device and the third device.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventor: Brent M. Sherman
  • Publication number: 20180278420
    Abstract: Embodiments of a system and method for creating a chain of trust are generally described herein. A method may include generating a private secret value, determining a public test value using the private secret value, sending, from a first device in a trusted environment with a second device and a third device, the public test value to the second device, receiving, at the first device outside the trusted environment, a challenge from the third device, determining a verification to the challenge using the private secret value, sending, from the first device outside the trusted environment, the verification to the second device, and receiving, at the first device outside the trusted environment, confirmation from the third device that the verification was successfully verified by the second device and the third device.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Inventor: Brent M. Sherman
  • Patent number: 10009185
    Abstract: Embodiments of a system and method for creating a chain of trust are generally described herein. A method may include generating a private secret value, determining a public test value using the private secret value, sending, from a first device in a trusted environment with a second device and a third device, the public test value to the second device, receiving, at the first device outside the trusted environment, a challenge from the third device, determining a verification to the challenge using the private secret value, sending, from the first device outside the trusted environment, the verification to the second device, and receiving, at the first device outside the trusted environment, confirmation from the third device that the verification was successfully verified by the second device and the third device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventor: Brent M. Sherman
  • Publication number: 20180097614
    Abstract: A method, computing system, and computer-readable medium comprising instructions to establish a chain of trust for components of a computing environment. A respective public/private key pair is generated using a multivariate quadratic function F for each component of the computing environment. In response to a challenge from a verifier, a current prover component sends a response that the verifier uses to determine whether to trust the current prover component. The response may include a first commitment value and a second commitment value, which are determined for the current prover component using a public key of a previous prover component. At least one of the first and second commitment values can be determined using a polar function G, which is a polar form of the multivariate quadratic function F.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventor: Brent M. Sherman
  • Patent number: 9740863
    Abstract: Embodiments of an invention for protecting a secure boot process against side channel attacks are disclosed. In one embodiment, an apparatus includes cryptography hardware, a non-volatile memory, a comparator, and control logic. The cryptography hardware is to operate during a first boot process. The non-volatile memory includes a storage location in which to store a count of tampered boots. The comparator is to perform a comparison of the count of tampered boots to a limit. The control logic is to, based on the first comparison, transfer control of the apparatus from the first boot process to a second boot process.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventor: Brent M. Sherman
  • Publication number: 20170180356
    Abstract: Embodiments of a system and method for creating a chain of trust are generally described herein. A method may include generating a private secret value, determining a public test value using the private secret value, sending, from a first device in a trusted environment with a second device and a third device, the public test value to the second device, receiving, at the first device outside the trusted environment, a challenge from the third device, determining a verification to the challenge using the private secret value, sending, from the first device outside the trusted environment, the verification to the second device, and receiving, at the first device outside the trusted environment, confirmation from the third device that the verification was successfully verified by the second device and the third device.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventor: Brent M. Sherman
  • Publication number: 20160378691
    Abstract: In one embodiment, an apparatus includes a storage controller to couple to a storage device. The storage controller may include a first counter to maintain a first count of incoming read requests to the storage device, a second counter to maintain a second count of incoming write requests to the storage device, and a workload analysis logic to calculate a workload ratio based at least in part on the first count and the second count, compare the workload ratio to an estimated workload ratio, and issue a tamper alert based at least in part on the comparison. Other embodiments are described and claimed.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventor: Brent M. Sherman
  • Publication number: 20160357963
    Abstract: Embodiments of an invention for protecting a secure boot process against side channel attacks are disclosed. In one embodiment, an apparatus includes cryptography hardware, a non-volatile memory, a comparator, and control logic. The cryptography hardware is to operate during a first boot process. The non-volatile memory includes a storage location in which to store a count of tampered boots. The comparator is to perform a comparison of the count of tampered boots to a limit. The control logic is to, based on the first comparison, transfer control of the apparatus from the first boot process to a second boot process.
    Type: Application
    Filed: November 25, 2014
    Publication date: December 8, 2016
    Inventor: Brent M. SHERMAN
  • Patent number: 9189617
    Abstract: An apparatus and method for zero knowledge proof security techniques within a computing platform. One embodiment includes a security module executed on a processing core to establish a domain of trust among a plurality of layers by sending a challenge from a verification layer to a first prover layer, the challenge comprising an indication of at least one selected option; in response to receiving the challenge, generating first verification information at the first prover layer based on the secret and the indication of the selected option; sending the first verification information to at least a second prover layer, the second prover layer generating second verification information based on the first verification information and the indication of the selected option; and performing a verification operation at the verification layer using the second verification information based on the selected option.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 17, 2015
    Assignee: INTEL CORPORATION
    Inventor: Brent M. Sherman
  • Publication number: 20150095655
    Abstract: An apparatus and method for zero knowledge proof security techniques within a computing platform. One embodiment includes a security module executed on a processing core to establish a domain of trust among a plurality of layers by sending a challenge from a verification layer to a first prover layer, the challenge comprising an indication of at least one selected option; in response to receiving the challenge, generating first verification information at the first prover layer based on the secret and the indication of the selected option; sending the first verification information to at least a second prover layer, the second prover layer generating second verification information based on the first verification information and the indication of the selected option; and performing a verification operation at the verification layer using the second verification information based on the selected option.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventor: Brent M. Sherman
  • Publication number: 20040059973
    Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a device under test (DUT) having a joint test access group (JTAG) port. The JTAG port may be accessed with a high speed and an integrated circuit adapted to access the JTAG port of the DUT.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Brent M. Sherman, Joshua J. Earl, Brian D. Redger