Abstract: Methods, systems, and switches for burst error correction of packets in a high-performance computing (‘HPC’) environment are provided. Embodiments include receiving, at a switch, one or more packets and one or more codewords associated with the one or more packets; determining, by the switch in dependence upon a link-level replay latency algorithm, whether forward error correction has higher latency than a link-level replay; and if link-level replay has less latency than forward error correction, requesting, by the switch, a link-level replay; and using forward error correction if forward error correction has less latency.

Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.

Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.

Abstract: Various embodiments are generally directed to dynamically changing a width of a network link without inactivating the network link. Provided are component communicatively coupled via a network link configured to negotiate a new network link width and to initiate a soft recovery of the network link to implement the new negotiated link width.

Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.

Abstract: One embodiment provides a mixed signal connector. The mixed signal connector includes a housing, a plurality of housing low-speed electrical contacts and a plurality of mixed-signal connector electrical contacts. The plurality of housing low-speed electrical contacts are to removably couple to a number of substrate electrical contacts. The plurality of mixed-signal connector electrical contacts are to removably couple to an external cable assembly. The plurality of mixed-signal connector electrical contacts includes a first subset to fixedly couple to a high-speed internal cable, and a second subset coupled to the plurality of housing low-speed electrical contacts.

Abstract: Various embodiments are generally directed to dynamically changing a width of a network link without inactivating the network link. Provided are component communicatively coupled via a network link configured to negotiate a new network link width and to initiate a soft recovery of the network link to implement the new negotiated link width.

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.

Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.

Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.

Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

Abstract: One embodiment provides a network controller. The network controller includes physical interface (PHY) circuitry comprising transmitter circuitry configured to transmit data frames to a link partner in communication with the transmit circuitry over a channel link. The network controller also includes a link speed cycling module configured to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed.