Abstract: The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Abstract: The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Abstract: A digital imaging system includes an array of sensors arranged generally in rows and columns and having data lines coupled to the sensors. Receiving logic is coupled to sense voltages on the data lines. A reference voltage generator (which can include a resistor network) generates a plurality of reference voltages in the digital imaging system in response to an applied differential voltage. A test row of sensors are electrically coupled to corresponding reference voltages, each test sensor coupled to a data line and receiving a voltage based on its coupled reference voltage. The receiving logic includes at least one A/D converter that reads the test sensor voltage value and converts it to a digital value.

Abstract: A jitter detection method and apparatus for informing an adaptive equalizer that the correlated jitter of transmitted data exceeds a predetermined jitter value. In one embodiment of the present invention, a jitter detection circuit receives transmitted data symbol pulses and clock signal pulses. The jitter detection circuit then compares a specified edge (e.g., the falling edge) of an incoming data pulse with the corresponding specified edge (e.g., the falling edge) of a clock signal pulse to determine if an original phase error between the incoming data pulse and the clock pulse exists. Similarly, the jitter detection circuit detect subsequent phase errors between subsequent data pulses and subsequent clock pulses. The original detected phase error will then be compared against subsequently detected phase errors. Based on this comparison of the phase errors, the jitter detection circuit then informs the adaptive equalizer of the degree of phase and amplitude compensation that it needs to provide.

Abstract: A circuit and method are provided for a pad efficient and speed efficient test of column leakage currents in silicon memory devices. Memory circuits are blocked into memory bit planes associated with individual I/O pins. Adequate testing requires that each column in each bit plane be tested for charge leakage characteristics. Rather than switching between I/O pins to test memory blocks associated with given pins, the switching circuitry is implemented on the silicon and is selectively coupled to the outputs of the bit planes on the chip. A single high voltage analog output pin is provided for test observations. This eliminates the need to ramp the testing system's voltages up and down and avoids the problems of hot switching between I/O pins.