Abstract: A method, system, and apparatus for reestablishing communications between a host and a service processor after the service processor has ceased to function correctly is provided. In one embodiment, the host exchanges heartbeat signals with the service processor. The heartbeat signals indicate that the service processor is active and functioning. In response to a failure to receive a heartbeat signal or in response to some other indication that the service processor is not performing correctly, the host causes a hard reset of the service processor. In addition, the service processor can detect a failure within itself and initiate a hard reset to itself. After the hard reset, the service processor returns to a monitoring mode without performing initial tests of the data processing system. Furthermore, the data processing system remains active and is not shut down during the hard reset of the service processor.

Abstract: A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for the page address and a least recently used (LRU) count; and the LRU count is updated for each access of the page address. Entries in the profiling cache are cast out using the LRU counts. A translation lookaside buffer (TLB) includes a first TLB section for storing a plurality of temporarily pinned entries and a second TLB section for storing a plurality of non-pinned entries. Responsive to a TLB interrupt, an entry is loaded in the second TLB section using a first in first out algorithm for replacing the non-pinned entries. The first TLB portion is periodically updated utilizing identified ones of the set of entries in the profiling cache having oldest time stamps.

Abstract: When a new control thread is initialized in a multi-thread software program, it is determined whether a like control thread has previously been instantiated. If so, a stack offset for the new control thread is set to be staggered from the stack offset for the previously instantiated like thread. By staggering the stack offsets of respective duplicate control threads, cache conflicts may be minimized.

Abstract: A method and computer program product are provided for partial paging and eviction of microprocessor instructions. Responsive to an instruction page fault, a predefined algorithm is applied to a virtual page address for the identified instruction page fault to identify a page table entry group within a volatile memory. Next, searching an identified page table entry group for a free or open page table entry is performed. Responsive to an identified open page table entry, a partial page is copied from a non-volatile memory to a corresponding partial page within the volatile memory.

Abstract: In a physical memory space, a pinned memory region is defined at one end of the space and a non-pinned region is defined at the other end of the space. A free region is between the pinned and non-pinned regions. Requests for pinned memory allocations are satisfied either by using holes in the pinned region or by appending the requested block to the end of the pinned region in the free region. The free region may be widened to accommodate pinned memory allocations. Requests for non-pinned memory allocations are satisfied by holes in the non-pinned region, by being appended to the non-pinned region in the free region or by filling holes in the pinned region, in that order.