Patents by Inventor Brenton F. Belmar
Brenton F. Belmar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10983833Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.Type: GrantFiled: July 31, 2019Date of Patent: April 20, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Matthias Klein, Peter G. Sutton
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Publication number: 20190354409Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.Type: ApplicationFiled: July 31, 2019Publication date: November 21, 2019Inventors: Brenton F. Belmar, Christian Jacobi, Matthias Klein, Peter G. Sutton
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Patent number: 10430246Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.Type: GrantFiled: January 18, 2018Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Matthias Klein, Peter G. Sutton
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Publication number: 20190220323Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.Type: ApplicationFiled: January 18, 2018Publication date: July 18, 2019Inventors: Brenton F. Belmar, Christian Jacobi, Matthias Klein, Peter G. Sutton
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Patent number: 10353759Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: May 15, 2018Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Publication number: 20180260263Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Inventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Patent number: 9983915Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: May 18, 2015Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Patent number: 9740549Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: June 15, 2012Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Patent number: 9442737Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: June 15, 2012Date of Patent: September 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Anthony Saporito, Timothy J. Slegel
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Patent number: 9442738Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: March 3, 2013Date of Patent: September 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Anthony Saporito, Timothy J. Slegel
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Patent number: 9367378Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: GrantFiled: March 3, 2013Date of Patent: June 14, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Patent number: 9311101Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.Type: GrantFiled: June 15, 2012Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Brenton F. Belmar, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
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Patent number: 9286076Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.Type: GrantFiled: October 21, 2014Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Brenton F. Belmar, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
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Publication number: 20150248317Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
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Publication number: 20150039868Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: Brenton F. Belmar, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
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Publication number: 20130339673Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
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Publication number: 20130339684Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Anthony Saporito, Timothy J. Slegel
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Publication number: 20130339327Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, TImothy J. Slegel
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Patent number: 8478922Abstract: The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.Type: GrantFiled: June 23, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Brenton F. Belmar, David Craddock, Janet R. Easton, Mark S. Farrell, Thomas A. Gregg, Damian L. Osisek, Donald W. Schmidt, Gustav E. Sittmann, III, Richard P. Tarcza
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Publication number: 20110320664Abstract: The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brenton F. Belmar, David Craddock, Janet R. Easton, Mark S. Farrell, Thomas A. Gregg, Damian L. Osisek, Donald W. Schmidt, Gustav E. Sittmann, III, Richard P. Tarcza