Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: An apparatus and method for adhesively bonding a back surface of a substrate to an active surface of at least one semiconductor die having adhesive tape interposed therebetween. A wetting agent layer is provided on at least one of the back surface of the substrate and the active surface of at least one semiconductor die. The wetting agent layer interacts with an adhesive on the adhesive tape when the substrate is heated so that the substrate is adhesively bonded to at least one semiconductor die. The interaction of the wetting agent layer allows the adhesive tape to bond thereto at a lower temperature than that of the conventional bonding methods, and more importantly, enhances adhesion thereto.

Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: An apparatus and method for adhesively bonding a back surface of a substrate to an active surface of at least one semiconductor die having adhesive tape interposed therebetween. A wetting agent layer is provided on at least one of the back surface of the substrate and the active surface of at least one semiconductor die. The wetting agent layer interacts with an adhesive on the adhesive tape when the substrate is heated so that the substrate is adhesively bonded to at least one semiconductor die. The interaction of the wetting agent layer allows the adhesive tape to bond thereto at a lower temperature than that of the conventional bonding methods, and more importantly, enhances adhesion thereto.

Abstract: An apparatus and method for adhesively bonding a back surface of a substrate to an active surface of at least one semiconductor die having adhesive tape interposed therebetween. A wetting agent layer is provided on at least one of the back surface of the substrate and the active surface of at least one semiconductor die. The wetting agent layer interacts with an adhesive on the adhesive tape when the substrate is heated so that the substrate is adhesively bonded to at least one semiconductor die. The interaction of the wetting agent layer allows the adhesive tape to bond thereto at a lower temperature than that of the conventional bonding methods, and more importantly, enhances adhesion thereto.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: An apparatus and method for adhesively bonding a back surface of a substrate to an active surface of at least one semiconductor die having adhesive tape interposed therebetween. A wetting agent layer is provided on at least one of the back surface of the substrate and the active surface of at least one semiconductor die. The wetting agent layer interacts with an adhesive on the adhesive tape when the substrate is heated so that the substrate is adhesively bonded to at least one semiconductor die. The interaction of the wetting agent layer allows the adhesive tape to bond thereto at a lower temperature than that of the conventional bonding methods, and more importantly, enhances adhesion thereto.

Abstract: An apparatus and method for adhesively bonding a back surface of a substrate to an active surface of at least one semiconductor die having adhesive tape interposed therebetween. A wetting agent layer is provided on at least one of the back surface of the substrate and the active surface of at least one semiconductor die. The wetting agent layer interacts with an adhesive on the adhesive tape when the substrate is heated so that the substrate is adhesively bonded to at least one semiconductor die. The interaction of the wetting agent layer allows the adhesive tape to bond thereto at a lower temperature than that of the conventional bonding methods, and more importantly, enhances adhesion thereto.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.