Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously.

Abstract: An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conductor. A high voltage power supply decoupling capacitor is coupled between the first and third power supply conductors. A low voltage power supply decoupling capacitor coupled between the first and second power supply conductors. A voltage reducer is coupled between the second and third power supply conductors. A plurality of semiconductor devices is biased between the first and second power supply conductors.

Abstract: An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conductor. A high voltage power supply decoupling capacitor is coupled between the first and third power supply conductors. A low voltage power supply decoupling capacitor coupled between the first and second power supply conductors. A voltage reducer is coupled between the second and third power supply conductors. A plurality of semiconductor devices is biased between the first and second power supply conductors.

Abstract: A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

Abstract: A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

Abstract: A circuit for measuring the frequency difference between a reference clock and a second clock. The circuit presents a first output in response to a phase crossing between the two clocks. A second circuit presents a second output in response to the first output and the reference clock.