Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include an interfacing die and at least one additional die communicatively coupled to each other through an internal bus. The interfacing die may be configured to provide a combined external interface for the coupled dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the at least one additional die.

Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a set of slave dies communicatively coupled to each other through an internal bus. The master die may be configured to provide a combined external interface for both the master die and the set of slave dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the set of slave dies.

Abstract: The present invention provides a system and method for utilizing profile information to set and maintain general and applications settings. In architecture, the system includes a computer device for performing the operation. The computer device comprises an operation module that determines an operation type and a setting module that determines the set of setting to perform the operation on the computer device. Moreover, the computer device further comprises an acquisition module that acquires the set of setting to perform the operation on the computer device. The present invention can also be viewed as a method for utilizing profile information to set and maintain general and applications settings. The method operates by (1) determining the operation on the computer device; (2) determining the set of setting to perform the operation on the computer device; and (3) acquiring the set of setting to perform the operation on the computer device.

Abstract: The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

Abstract: A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

Abstract: The present invention provides a system and method for utilizing profile information to set and maintain general and applications settings. In architecture, the system includes a computer device for performing the operation. The computer device comprises an operation module that determines an operation type and a setting module that determines the set of setting to perform the operation on the computer device. Moreover, the computer device further comprises an acquisition module that acquires the set of setting to perform the operation on the computer device. The present invention can also be viewed as a method for utilizing profile information to set and maintain general and applications settings. The method operates by (1) determining the operation on the computer device; (2) determining the set of setting to perform the operation on the computer device; and (3) acquiring the set of setting to perform the operation on the computer device.

Abstract: The present invention provides a system and method for parsing itinerary data on a computing device. In architecture, the system includes a data acquisition module that acquires itinerary data and a parsing module that parses the itinerary data into the a computer readable itinerary data. The system further includes a generation module that generates a predefined user form with the computer readable itinerary data. The present invention can also be viewed as a method for parsing itinerary data on a computing device. The method operates by (1) providing itinerary data; (2) parsing the itinerary data into a computer readable itinerary data; and (3) generating a predefined user form with the computer readable itinerary data.

Abstract: A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

Abstract: The present invention provides a system and method for providing remote device data synchronization. In architecture, the system includes a remote device with a device data, a server device containing an original data and a revision data of the original data, and a delta data that identifies only the changes between the original data and the revision data. The present invention can also be viewed as a method for transmitting data that is modified on a server to a remote device. The method operates by (1) providing an original data; (2) creating update data of the original data; and (3) generating a delta data that identifies only the changes between the original data and the updated data; and (4) transmitting the delta data to a remote device.

Abstract: Binary information is written to and read from a memory cell field forming a matrix-type field of rows and columns via a plurality of write/read circuits, each having a latch flipflop with at least one data terminal connected on one side to an allocated column-related bit line and on the other side, by way of a gate circuit, to a data line. Access to the relevant bit line is accomplished via a column selection signal which controls the gate circuit. A switching device facilitates the writing process. After the excitation of any row-related word line, the switching device interrupts the current supply of the latch flipflops that are selected for an access starting no earlier than when the relevant latch flipflop assumes a state indicating the information content of the accessed memory cell and, at the latest, during the active interval of the relevant column selection signal.

Abstract: A refresh drive circuit for feeding refresh signals to a memory device has a refresh signal generator for generating a continuous sequence of refresh signals with a frequency which decreases as the temperature falls. The refresh drive circuit is connected to the memory device and as the temperature of the memory device falls, the frequency of refresh cycles decreases resulting in a decrease in current consumption.

Abstract: Binary information is written to and read from a memory cell field forming a matrix-type field of rows and columns via a plurality of write/read circuits, each having a latch flipflop with at least one data terminal connected on one side to an allocated column-related bit line and on the other side, by way of a gate circuit, to a data line. Access to the relevant bit line is accomplished via a column selection signal which controls the gate circuit. A switching device facilitates the writing process. After the excitation of any row-related word line, the switching device interrupts the current supply of the latch flipflops that are selected for an access starting no earlier than when the relevant latch flipflop assumes a state indicating the information content of the accessed memory cell and, at the latest, during the active interval of the relevant column selection signal.

Abstract: A refresh drive circuit for feeding refresh signals to a memory device has a refresh signal generator for generating a continuous sequence of refresh signals with a frequency which decreases as the temperature falls. The refresh drive circuit is connected to the memory device and as the temperature of the memory device falls, the frequency of refresh cycles decreases resulting in a decrease in current consumption.

Abstract: An integrated semiconductor memory having memory cells (MC) for storing data signals (DQ), has a memory sense amplifier (2) with an input (21) for a data signal (DQ) of one of the memory cells (MC), and an output (23) for at least one output signal (RD0). A driver circuit (3) is connected to the output (23) of the memory sense amplifier (2). The driver circuit (3) can be activated or deactivated only by the output signal (RD0) of the memory sense amplifier (2). A signal line (4) is connected to the driver circuit (3), a precharging circuit (5) and to a memory circuit (6). A terminal (7) for a control signal (C) is connected to the memory sense amplifier (2), the precharging circuit (5) and the memory circuit (6). As result of a driver circuit (3) which has a relatively low level of circuit complexity, the space requirements are kept relatively small. In addition, high switching speeds are made possible during the reading operation.

Abstract: An integrated semiconductor memory having memory cells (MC) for storing data signals (DQ), has a memory sense amplifier (2) with an input (21) for a data signal (DQ) of one of the memory cells (MC), and an output (23) for at least one output signal (RD0). A driver circuit (3) is connected to the output (23) of the memory sense amplifier (2). The driver circuit (3) can be activated or deactivated only by the output signal (RD0) of the memory sense amplifier (2). A signal line (4) is connected to the driver circuit (3), a precharging circuit (5) and to a memory circuit (6). A terminal (7) for a control signal (C) is connected to the memory sense amplifier (2), the precharging circuit (5) and the memory circuit (6). As result of a driver circuit (3) which has a relatively low level of circuit complexity, the space requirements are kept relatively small. In addition, high switching speeds are made possible during the reading operation.

Abstract: An output driver circuit of a clocked integrated semiconductor memory of the DRAM type is driven by a circuit for generating an output signal as a function of two input signals. A validity signal, which is supplied to the circuit, ensures that the data to be output are in a valid state before the output driver is activated. As a result, a situation in which different propagation times of input signals of the output driver circuit lead to multiple switching operations within an access cycle of a memory access is prevented. An event-oriented control of the enabling process of the output driver ensures a proper function even in the case of variable frequencies of the clock control.

Abstract: The digital memory has at least one data line and address lines. It also has a switching unit that, in an active state, inverts signals on the data line or on at least one of the address lines and that, in an inactive state, leaves the signals unchanged. In a first operating mode, the switching unit is in the same state for writing and reading. In a second operating mode, the switching unit is in respectively opposite states for writing and for reading.

Abstract: The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Abstract: A dynamic semiconductor memory device of the random access type having an initialization circuit which controls the switch-on operation of the semiconductor memory device and of its circuit components. The initialization circuit supplies a supply voltage stable signal once the supply voltage has been stabilized after the switching-on of the semiconductor memory device. The initialization circuit has an advance detector circuit, which detects a predetermined level state of an externally applied clock control signal chronologically before the supply voltage stable signal is generated and, as a reaction to this, supplies a first enable signal for unlatching the control circuit provided for the proper operation of the semiconductor memory device.

Abstract: A pulse shaper circuit includes a buffer having an input, an output and two supply connections. A controllable first switch is connected between one of the supply connections and a first supply potential, a controllable second switch is connected between the other supply voltage connection and a second supply potential, a controllable third switch is connected between the output of the buffer and the first supply potential and a controllable fourth switch is connected between the output of the buffer and the second supply potential. A control device for the switches is connected to the output of the buffer and produces a first control pulse of a specific duration at the occurrence of first edges of a signal present at the output of the buffer and a second control pulse of a specific duration at the occurrence of second edges. The first control pulse changes over the first switch from the ON state to the OFF state and the fourth switch from the OFF state to the ON state.