Abstract: A technique for accounting for resource usage time by virtual machines is provided according to which a virtual machine observes a non-virtual timer to determine an elapsed non-virtual time interval during which the virtual machine performed a computation while using a shared processing resource. The virtual machine infers the amount of time it used the shared processing resource based on the observation.

Abstract: A virtual machine is migrated from a first physical machine to a second physical machine in response to a failure of an instruction to execute. A migration constraint also is created which limits future migration of the virtual machine by a placement controller to only those physical machines that can execute the failed instruction.

Abstract: In various embodiments of the present invention, execution-state transitions occur in a first portion of a system, and a cumulative execution state for each process is maintained by a second portion of the system so that, when a second-portion routine is called, the second-portion routine can determine whether or not the current execution state is suitable for execution of the second-portion routine. In various embodiments, a callpoint log, allocated and maintained for each process, stores the cumulative execution state for the process. In one embodiment, the first portion is an operating system, and the second portion is a secure kernel, with the cumulative execution state used by the secure kernel to prevent unauthorized access by erroneously or maliciously invoked operating-system routines to secure kernel routines. In another embodiment, the cumulative execution state is used as a debugging tool by the second-portion routines to catch errors in the implementation of the first-portion routines.

Abstract: A system for managing resources automatically among nodes includes a node controller configured to dynamically manage allocation of node resources to individual workloads, where each of the nodes is contained in one of a plurality of pods. The system also includes a pod controller configured to manage live migration of workloads between nodes within one of the plurality of pods, where the plurality of pods are contained in a pod set. The system further includes a pod set controller configured to manage capacity planning for the pods contained in the pod set. The node controller, the pod controller and the pod set controller are interfaced with each other to enable the controllers to meet common service policies in an automated manner. The node controller, the pod controller and the pod set controller are also interfaced with a common user interface to receive service policy information.

Abstract: A method is provided for evaluating workload consolidation on a computer located in a datacenter. The method comprises inflating a balloon workload on a first computer that simulates a consolidation workload of a workload originating on the first computer and a workload originating on a second computer. The method further comprises evaluating the quality of service on the first computer's workload during the inflating and transferring the workload originating on either the first or the second computer to the other of the first or second computer if the evaluating the quality of service remains above a threshold.

Abstract: Various embodiments of the present invention introduce privilege-level mapping into a computer architecture not initially designed for supporting virtualization. Privilege-level mapping can, with relatively minor changes to processor logic, fully prevent privileged-level-information leaks by which non-privilege code can determine the current machine-level privilege level at which they are executing. In one embodiment of the present invention, a new privilege-level mapping register is introduced, and privilege-level mapping is enabled for all but code invoked by privileged-level-0-forcing hardware events.

Abstract: A command is received to place a first physical machine into a lower power mode. The first physical machine has a virtual machine. In response to the received command, a procedure is performed to migrate the virtual machine from the first physical machine to a second physical machine.

Abstract: A system has plural physical machines that contain virtual machines. A load balancer receives a request from a client. In response to the request, it is determined whether at least one additional virtual machine should be started up. In response to determining that at least one additional virtual machine should be started up, the load balancer sends at least one command to start up the at least one additional virtual machine in at least one of the physical machines.

Abstract: A combined-hardware-and-software secure-platform interface to which operating systems and customized control programs interface within a computer system. The combined-hardware-and-software secure-platform interface employs a hardware platform that provides at least four privilege levels, non-privileged instructions, non-privileged registers, privileged instructions, privileged registers, and firmware interfaces. The combined-hardware-and-software secure-platform interface conceals all privileged instructions, privileged registers, and firmware interfaces and privileged registers from direct access by operating systems and custom control programs, providing to the operating systems and custom control programs the non-privileged instructions and non-privileged registers provided by the hardware platform as well as a set of callable software services.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: Various embodiments of the present invention introduce privilege-level mapping into a computer architecture not initially designed for supporting virtualization. Privilege-level mapping can, with relatively minor changes to processor logic, fully prevent privileged-level-information leaks by which non-privilege code can determine the current machine-level privilege level at which they are executing. In one embodiment of the present invention, a new privilege-level mapping register is introduced, and privilege-level mapping is enabled for all but code invoked by privileged-level-0-forcing hardware events.

Abstract: A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

Abstract: A networked system includes a fault tolerant storage system (FTSS) having an interconnection fabric that also carries network traffic. A plurality of servers are coupled to an FTSS via an FTSS interconnection fabric. As soon as a packet is received from a sending node, the packet is committed to reliable, persistent, and fault-tolerant storage media within the FTSS, and will not be lost. If the destination node is one of the servers coupled to the FTSS, the FTSS can send an acknowledgment to the sending node guaranteeing delivery to the destination node, even though the destination node has not yet received the packet. The packet is then transmitted to the receiving node, with the receiving node sending an acknowledgment to the FTSS when the packet has been received successfully.

Abstract: In various embodiments of the present invention, execution-state transitions occur in a first portion of a system, and a cumulative execution state for each process is maintained by a second portion of the system so that, when a second-portion routine is called, the second-portion routine can determine whether or not the current execution state is suitable for execution of the second-portion routine. In various embodiments, a callpoint log, allocated and maintained for each process, stores the cumulative execution state for the process. In one embodiment, the first portion is an operating system, and the second portion is a secure kernel, with the cumulative execution state used by the secure kernel to prevent unauthorized access by erroneously or maliciously invoked operating-system routines to secure kernel routines. In another embodiment, the cumulative execution state is used as a debugging tool by the second-portion routines to catch errors in the implementation of the first-portion routines.

Abstract: A method and apparatus pass messages between server and client applications using a fault tolerant storage system (FTSS). The interconnection fabric that couples the FTSS to the computer systems that host the client and server applications may also be used to carry messages. A networked system capable of hosting a distributed application includes a plurality of computer systems coupled to an FTSS via an FTSS interconnection fabric. The FTSS not only processes file-related I/O transactions, but also includes several message agents to facilitate message transfer in a reliable and fault tolerant manner. The message agents include a conversational communication agent, an event-based communication agent, a queue-based communication agent, a request/reply communication agent, and an unsolicited communication agent. The highly reliable and fault tolerant nature of the FTSS ensures that the FTSS can guarantee delivery of a message transmitted from a sending computer system to a destination computer system.

Abstract: A system monitors unaligned memory accesses by a processor of a computer system. The processor automatically generates a fault when attempting an unaligned memory access. Unaligned memory access faults are disabled in response to a fault generated by a first faulting instruction. The first faulting instruction is executed. A trap is generated by executing the first faulting instruction. Unaligned memory access faults are enabled in response to the trap.

Abstract: Method and system for controlling areas of memory within a computer system to routines executing at a specific privilege levels in a modern computer architecture featuring protection keys, operating-system-routine calls and interrupts result in promotion of the current privilege level to the highest privilege level prior to dispatch to an operating system routine with concomitant demotion of the CPL Current Privilege Level to operating-system-privilege level. By partitioning the 24-bit protection queue space into multiple protection-key domains, each protection-key domain associated with a privilege level, and by invalidating protection-key registers during each protection of the current privilege level to a higher privilege level, regions of memory are provided that can only be accessed by routines running at low privilege levels and by routines at the highest privilege level, but not accessible to routines running at intermediate privilege levels.

Abstract: A system monitors the execution of privileged instructions by a processor of a computer system. The processor includes a current privilege level. The processor automatically generates a fault when attempting execution of an instruction requiring a higher privilege level than the current privilege level of the processor. The current privilege level of the processor is raised in response to a fault generated by a first faulting instruction. The first faulting instruction is executed. A trap is generated by executing the first faulting instruction. The current privilege level of the processor is lowered in response to the trap.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: Method and system for providing hardware-enforced synchronization and serialization mechanisms, such as semaphores, to allow for control of access to memory regions within a computer system. In addition to the traditional semaphore protocol, hardware enforced semaphores are associated with memory regions and with protection keys selected from a pool of protection keys that control access to those memory regions. Hardware-enforced semaphores control insertion and deletion of protection keys from protection-key registers and internal data structures in order to enforce access grants provided by the semaphore protocol.