Abstract: A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.

Abstract: A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.

Abstract: A testing circuit for verifying the impedance of off-chip drivers includes: a plurality of off-chip drivers (OCD), each off-chip driver including a through-silicon via (TSV); an IREF test pad, for driving a current to the plurality of off-chip drivers; a plurality of pre-drivers, each respective pre-driver coupled to one of the plurality of off-chip drivers, wherein the plurality of pre-drivers are configured to turn on the off-chip drivers; a VREF test pad, for inputting a reference voltage to the testing circuit; a plurality of input buffers (IB) for outputting a plurality of comparison results, each of the plurality of input buffers configured to output the plurality of comparison results according to the reference voltage and the voltage at the TSV nodes; and a test pad, coupled to the plurality of IBs, for receiving the comparison results to determine whether the impedance of each OCD is within a desired range.

Abstract: A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.

Abstract: A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.

Abstract: A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.

Abstract: A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.

Abstract: An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.

Abstract: A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.

Abstract: A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.

Abstract: A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.

Abstract: A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.

Abstract: A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.

Abstract: A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.

Abstract: An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.