Patents by Inventor Bret Siarowski

Bret Siarowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for logic equivalence checking
    Patent number: 7620919
    Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin
  • Method and system for logic equivalence checking
    Patent number: 7620918
    Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin