Patents by Inventor Bret Stott
Bret Stott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9257163Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: August 5, 2013Date of Patent: February 9, 2016Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20160012869Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: September 23, 2015Publication date: January 14, 2016Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 9165617Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: January 13, 2014Date of Patent: October 20, 2015Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20140173240Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: January 13, 2014Publication date: June 19, 2014Applicant: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20140140149Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: August 5, 2013Publication date: May 22, 2014Applicant: Rambus Inc.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 8638637Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: December 19, 2012Date of Patent: January 28, 2014Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 8504788Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: December 19, 2007Date of Patent: August 6, 2013Assignee: Rambus Inc.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 8378699Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.Type: GrantFiled: April 27, 2009Date of Patent: February 19, 2013Assignee: Rambus Inc.Inventors: Bret Stott, Philip Yeung, John W. Brooks, Benedict Lau, Chanh V. Tran, Eugene C. Ho
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Patent number: 8339878Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: December 23, 2011Date of Patent: December 25, 2012Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20120188835Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: December 23, 2011Publication date: July 26, 2012Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 8089824Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: June 3, 2009Date of Patent: January 3, 2012Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20100039875Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: December 19, 2007Publication date: February 18, 2010Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20090238025Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: June 3, 2009Publication date: September 24, 2009Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20090206867Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.Type: ApplicationFiled: April 27, 2009Publication date: August 20, 2009Inventors: Bret Stott, Philip Yeung, John W. Brooks, Benedict Lau, Chanh V. Tran, Eugene C. Ho
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Patent number: 7558150Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: June 25, 2007Date of Patent: July 7, 2009Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 7535242Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.Type: GrantFiled: May 3, 2006Date of Patent: May 19, 2009Assignee: Rambus Inc.Inventors: Bret Stott, Philip Yeung, John W. Brooks, Benedict Lau, Chanh V. Tran, Eugene C. Ho
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Patent number: 7321524Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: October 17, 2005Date of Patent: January 22, 2008Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20070257693Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.Type: ApplicationFiled: May 3, 2006Publication date: November 8, 2007Inventors: Bret Stott, Philip Yeung, John Brooks, Benedict Lau, Chanh Tran, Eugene Ho
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Publication number: 20070247961Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: June 25, 2007Publication date: October 25, 2007Inventors: Ian Shaeffer, Bret Stott, Benedict Lau
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Publication number: 20070217559Abstract: An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sampling circuit samples a data signal in response to the timing signal to generate a sequence of data samples, and also samples the data signal in response to a phase-shifted version of the timing signal to generate a sequence of edge samples. The delay control circuit adjusts the first interval based, at least in part, on a phase error indicated by the sequence of data samples and the sequence of edge samples.Type: ApplicationFiled: March 16, 2006Publication date: September 20, 2007Inventors: Bret Stott, Craig Hampel, Frederick Ware