Abstract: An integrated circuit (IC) package comprises a substrate having an outer portion close to the perimeter of the substrate, an inner portion surrounded by the outer portion, and an upper surface incorporating a wiring layer for the bonding of a semiconducting die (e.g., via its bottom face). The IC package includes a metallic or otherwise thermally conductive heat spreader thermally bonded on an inner surface of a boss on its bottom side to the top surface of the semiconducting die, and extending on its top surface to the edges of the substrate to maximize heat dissipation from the die. The boss extends toward the semiconducting die and is thermally coupled to the top face of the semiconducting die.

Abstract: A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

Abstract: A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

Abstract: A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas.

Abstract: A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

Abstract: A system and method includes pre-warping a mask to induce strain when affixed to a substrate and ensure positive contact between the mask and the substrate during all phases of deposition. A film is applied to the mask at a rate sufficient to impart stress to the film faster than such stress can be released. Depending on the features defined by the mask, the pre-warping may be concentric, linear along one axis, or complex along a plurality of axes.

Abstract: An electronic device fabrication system may include, but is not limited to: a conductive material deposition device configured for deposition of a conductive material; at least one electronic device substrate configured to receive deposited conductive material; and at least one mask configured to selectively transmit the conductive material to the electronic device substrate, wherein the at least one mask configured to selectively transmit the conductive material to the electronic device substrate includes: at least a first side disposed at an angle relative to an adjacent second side.

Abstract: A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

Abstract: A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A a surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

Abstract: A system and method includes pre-warping a mask to induce strain when affixed to a substrate and ensure positive contact between the mask and the substrate during all phases of deposition. A film is applied to the mask at a rate sufficient to impart stress to the film faster than such stress can be released. Depending on the features defined by the mask, the pre-warping may be concentric, linear along one axis, or complex along a plurality of axes.

Abstract: An interconnect assembly includes a spacer assembly including a top surface and a bottom surface; and a flexible circuit member including a first surface and a second surface opposite the first surface. The flexible circuit member curves about at least a portion of the spacer assembly such that a first portion of the first surface of the flexible circuit member is coupled to the top surface of the spacer assembly and a second portion of the first surface of the flexible circuit member is coupled to the bottom surface of the spacer assembly. The interconnect assembly further includes at least one top electrical interface element coupled to a first portion of the second surface of the flexible circuit member; and at least one bottom electrical interface element coupled to a second portion of the second surface of the flexible circuit member. The first portion of the second surface of the flexible circuit member is spaced apart from the second portion of the second surface of the flexible circuit member.

Abstract: An interposer and a method for stacking dies utilizing such an interposer in an integrated circuit are disclosed. The interposer includes a substrate and a plurality of vias defined in the substrate. At least one of the plurality of vias of the interposer is positioned to establish a connection with at least one of the plurality of vias of a first die. At least one additional die is positioned to establish a connection with the first die utilizing the connection established between the interposer and the first die through at least one of the vias.