Patents by Inventor Brett A. McClellan

Brett A. McClellan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Communication system and encoding method having low overhead
    Publication number: 20060256875
    Abstract: A communication system processes blocks of input data that include control words and a packet of information words are received. The packet has a start preceded by ones of the control words and an end followed by others of the control words. When the block consists exclusively of information words, a one bit block header having a first sense is appended to the block to form a frame. When the block does not consist exclusively of information words, the block is condensed to accommodate a TYPE word, the TYPE word is generated and inserted into the block and a one bit block header is appended to the block to form the frame. When the block does not consist exclusively of information words the one bit block header has a second sense, opposite to the first sense. Use of a one bit block header reduces overhead. Forward error correction is also utilized.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 16, 2006
    Inventor: Brett McClellan
  • Pin layer reversal detection
    Patent number: 6909567
    Abstract: A circuit to detect pin layer reversal including an input circuit to receive an input signal having a first portion to indicate a pin layer reversal and having a second portion to indicate a servo sync mark, a first servo sync mark detector for detecting a positive servo sync mark from the input signal, a second servo sync mark detector for detecting a negative servo sync mark from the input signal, and a circuit responsive to the positive servo sync mark and the negative servo sync mark to generate a signal to indicate if the servo sync mark has been reversed and to generate a signal to indicate the pin layer reversal.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: June 21, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Brett A. McClellan, Zubir Adal
  • Detection error estimation and method
    Patent number: 6735724
    Abstract: A method of monitoring the performance of a Viterbi detector by using the deviations from the noiseless case of the path difference of the two branches entering the minimal state for a number of samples.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Brett A. McClellan
  • Pin layer reversal detection
    Publication number: 20020063984
    Abstract: A circuit to detect pin layer reversal including an input circuit to receive an input signal having a first portion to indicate a pin layer reversal and having a second portion to indicate a servo sync mark, a first servo sync mark detector for detecting a positive servo sync mark from the input signal, a second servo sync mark detector for detecting a negative servo sync mark from the input signal, and a circuit responsive to the positive servo sync mark and the negative servo sync mark to generate a signal to indicate if the servo sync mark has been reversed and to generate a signal to indicate the pin layer reversal.
    Type: Application
    Filed: October 29, 2001
    Publication date: May 30, 2002
    Inventors: Brett A. McClellan, Zubir Adal
  • Runlength-limited code and method
    Patent number: 6285302
    Abstract: A method to create runlength-limited codes from shorter codes having suppression of error propagation by insertion of uncoded bits adjacent error suppression end bits of the shorter code.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: September 4, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Brett A. McClellan
  • Parity insertion with precoder feedback in a read channel
    Patent number: 6282690
    Abstract: A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: August 28, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Brett McClellan, Michael Leung, Leo Fu, Taehyun Jeon
  • Parity insertion with precoder feedback in a PRML read channel
    Patent number: 6243847
    Abstract: A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: June 5, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Brett McClellan, Michael Leung, Leo Fu, Taehyun Jeon