Patents by Inventor Brett D. Niver

Brett D. Niver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8996821
    Abstract: Methods and systems are disclosed for providing resource sharing in a computing environment using file descriptor isomorphism. The methods and systems may perform a method in a computing environment having processor systems executing processes. The method may include receiving a request from a first process to access a first resource. Further, the method may include generating a first Global File Descriptor (GFD) that references a first entry in a GFD table, the first GFD entry including a reference to a first entry in a resource descriptor table pointing to the first resource. Based on the request, at least one GFD field associated with the first GFD entry is configured. Thus, methods and systems may manage access by the first process to the first resource using the first GFD entry.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: March 31, 2015
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 8085794
    Abstract: Described are techniques for determining a set of routing information for a plurality of components performing routing in a network. Destinations that are directly connected to each of the plurality of components are determined. Each of the plurality of components is associated with one of a plurality of routing tables. Each of the plurality of routing tables stores routing information in accordance with destinations in the network. Cost information is stored in the plurality of routing tables for each destination directly connected to one of the plurality of components. For each of the plurality of components, a set of neighboring components is determined. For each neighboring component, routing information for a destination is adopted from the routing table of said each neighboring component in accordance with an adoption rule. Processing is repeatedly performed until the routing tables have not been modified.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 27, 2011
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, William F. Baxter, III, Steven R. Chalmer
  • Patent number: 7996848
    Abstract: In a methods and systems of controlling a process's access to a device driver, a lock may be used to establish a process wait state or to wake up one or more processes. A spinlock may be used to acquire a lock associated with a device driver. The lock includes a lock value representing the availability of the lock. If the lock value is a first value, the process acquires the lock and sets the lock value to a second value. Otherwise, the process returns to the step of using the spinlock to acquire the lock associated with the device driver. If the lock is acquired, the process accesses the device driver. If the device is not ready, the process is set to wait for the lock. Waiting for the lock comprises setting a field of the process to a pointer to the lock and setting a state of the process to waiting. After the device has been successfully accessed or the process has been set to wait for the lock, the lock is released typically by setting the lock value to the first value.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: August 9, 2011
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7853716
    Abstract: A data storage system having a packet switching network, a cache memory, and a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors and cache memory are interconnected through the packet switching network. Each one of the directors is adapted to transmit different types of information packets to another one of the directors through the network. Each one of the directors is adapted to transmit and receive different types of information packets to another one of the directors or cache memories through the packet switching network. Each one of the cache memories is adapted to receive and transmit different types of information packets to one of the directors through the packet switching network. One type of information packet requires a different degree of latency than another type of information packet.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: December 14, 2010
    Assignee: EMC Corporation
    Inventors: William F. Baxter, III, Stephen D. MacArthur, Man Min Moy, Brett D. Niver, Yechiel Yochai
  • Patent number: 7818447
    Abstract: Described is an end-to-end broadcast-based messaging technique used in controlling message flow in a data storage system. Each node stores flow control state information about all the nodes which is used in determining whether to send a data transmission to a receiving node. The flow control state information includes an indicator as to whether each node is receiving incoming data transmissions. If a node is not receiving incoming data transmissions, the flow control state information also includes an associated expiration time. Data transmissions are resumed to a receiving node based on the earlier of a sending node determining that the expiration time has lapsed, or receiving a control message from the receiving node explicitly turning on data transmissions. Each node maintains and updates its local copy of the flow control state information in accordance with control messages sent by each node to turn on and off data transmissions.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: October 19, 2010
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure, Stephen D. MacArthur, Avinash Kallat
  • Patent number: 7810094
    Abstract: A process scheduling method includes executing a plurality of symmetric schedulers on respective processors of a multiprocessing system. Each scheduler periodically accesses a shared lock to obtain exclusive access to a shared scheduling data structure including (a) process information identifying the processes, and (b) scheduling information reflecting the executability and priorities of the processes. After obtaining the lock, each scheduler performs a scheduling routine including (a) utilizing the scheduling information and a scheduling algorithm to identify a next executable process, and (b) (1) activating the identified process to begin executing on the processor on which the scheduler is executing, and (2) updating the scheduling information to reflect the activation of the identified process. The scheduler then accesses the lock to relinquish exclusive access to the scheduling data structure.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 5, 2010
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7793160
    Abstract: Methods and systems consistent with the present invention may facilitate error tracing in computer software. Such methods and systems may maintain context information of a target process, swap from a context of the target process to a context of an error-tracing process, and trace an error from the target process using the error-tracing process and the context information of the target process.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: September 7, 2010
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7720666
    Abstract: A method for determining throughput of a data passing between end points of a data communication system as a function of bit error rate, comprising: generating a mathematical model of the functional relationship between the throughput of data passing from a transmitting one of a pair of end points of a data communication system and a receiving one of the pair of end points and a bit error rate of data received at the receiving one of the pair of end points.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 18, 2010
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Qin Wang, Mohammad Faisal Siddiqui
  • Patent number: 7672303
    Abstract: A method is provided for performing arbitration in an information packet controller. The method includes transmitting different types of information packets from an initiator to a receiver. One type of information packet has a quality of service requiring a faster transmission time from the initiator to the receiver than another type of information packet having a quality of service having a slower transmission time from the initiator to the receiver. The transmitting of the information packets from the initiator to the receiver is in accordance with priority assigned to the information packet, the quality of service assigned to the information packet, and the age of such information packets having been stored in a queue of the initiator, such quality of service being a function of the speed at which the packets are required to pass from the initiator to a receiver.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: March 2, 2010
    Assignee: EMC Corporation
    Inventors: William F. Baxter, III, Stephen D. MacArthur, Man Min Moy, Brett D. Niver, Yechiel Yochai
  • Patent number: 7673100
    Abstract: Methods and systems are disclosed that relate to locating cached data corresponding to data in persistent memory within a data storage facility. An exemplary method includes receiving a request for data in persistent memory, applying a function to a persistent memory address of the requested data to determine an address of one of a plurality of cache tag controllers, each of which controls nonduplicative cache tags, and looking up, at the addressed cache tag controller, a cache memory address for data corresponding to the requested data.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: March 2, 2010
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 7552282
    Abstract: Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: June 23, 2009
    Assignee: EMC Corporation
    Inventors: Michael Bermingham, Kendell A. Chilton, Robert DeCrescenzo, Mark J. Halstead, Haim Kopylovitz, Steven T. McClure, James M. McGillis, Ofer E. Michael, Brett D. Niver, John K. Walton
  • Patent number: 7478202
    Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 13, 2009
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Publication number: 20080162863
    Abstract: Managing memory includes subdividing the memory into a first set of blocks corresponding to a first size and a second set of blocks corresponding to a second size that is greater than said first size, in response to a request for an amount of memory that is less than or equal to the first size, providing one of the first set of blocks, and, in response to a request for an amount of memory that is greater than the first size and less than or equal to the second size, providing one of the second set of blocks. Subdividing the memory may also include subdividing the memory into a plurality of sets of blocks, where each particular set contains blocks corresponding to one size that is different from that of blocks not in the particular set. Each set of blocks may correspond to a size that is a multiple of a predetermined value. Managing memory may also include providing a table containing an entry for each set of blocks. The entry for each set of blocks may be a pointer to one of: an unused block and null.
    Type: Application
    Filed: December 13, 2007
    Publication date: July 3, 2008
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7392361
    Abstract: Managing memory includes receiving a request for a memory allocation, determining whether the memory allocation is to be maintained when subsequently initializing memory and saving information about the memory allocation to maintain the memory allocation during subsequently initializing memory. Initializing may be performed as part of special reset mode processing. Special reset mode processing may be performed in response to receiving a reset command. The memory may be shared by a plurality of processing units and the reset command may be issued to reset a first processing unit causing reset of the memory and a second processing unit may use a first allocated memory portion that is maintained when initializing the memory as part of processing for the reset command. Saving may include adding an entry to an allocation list associated with the memory, the entry including a location associated with the memory allocation.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: June 24, 2008
    Assignee: EMC Corporation
    Inventors: David L. Reese, Steven R. Chalmer, Steven T. McClure, Brett D. Niver
  • Patent number: 7363431
    Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: April 22, 2008
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 7343432
    Abstract: Described is a distributed lock processing technique that may be used to coordinate access to globally accessed resource between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. Each endpoint, prior to requesting a lock, dynamically determines a current lock owner of the lock to be requested in accordance with a determination of which endpoints are available as lock owners at the current time. The lock request is issued to the current lock owner with a requested time period used by the lock owner to determine an expiration time. The lock expires automatically at the expiration time even if the lock holder becomes unavailable. If the current lock owner becomes unavailable, a new lock owner is determined prior to the next request for that lock.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: March 11, 2008
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 7330956
    Abstract: Managing memory includes subdividing the memory into a first set of blocks corresponding to a first size and a second set of blocks corresponding to a second size that is greater than said first size, in response to a request for an amount of memory that is less than or equal to the first size, providing one of the first set of blocks, and, in response to a request for an amount of memory that is greater than the first size and less than or equal to the second size, providing one of the second set of blocks. Subdividing the memory may also include subdividing the memory into a plurality of sets of blocks, where each particular set contains blocks corresponding to one size that is different from that of blocks not in the particular set. Each set of blocks may correspond to a size that is a multiple of a predetermined value. Managing memory may also include providing a table containing an entry for each set of blocks. The entry for each set of blocks may be a pointer to one of: an unused block and null.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: February 12, 2008
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7178146
    Abstract: Described are techniques used in task scheduling to form a run list used by a task scheduler. A non-priority based technique is disclosed in which each task to be executed is allotted a “pie” count representing the number of times out of the total run list each task is considered for scheduling. The total run list is the sum of all the “pie” counts for all tasks. Each time a task starts, exits, or has its pie count reset, the total number of “pie” counts is computed and tasks are distributed throughout the run list. Each task is distributed in the run list in accordance with its number of “pie” counts such that a minimum number of intervening tasks appears between each successive appearance of the same task. The computed run list is then used by the scheduler. The task scheduling techniques disclosed may be used in a data storage system or elsewhere in a computer system.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 13, 2007
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7136969
    Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 14, 2006
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 6757790
    Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: June 29, 2004
    Assignee: EMC Corporation
    Inventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver, Richard G. Wheeler