Abstract: A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device.

Abstract: An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at the respective each module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at the respective each module, indicate to the respective other module that the respective each module is ready to exit the reset mode and exit the reset mode when the respective other module has also indicated that the respective other module is ready to exit the reset mode.

Abstract: A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device.

Abstract: An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO buffer which includes a plurality of buffer slices including an output buffer slice wherein each of the plurality of buffer slices comprise a data register and a control bit register. A buffer slice is identified which is indicated for storing a data element based on a control bit register for the buffer slice and a control bit register of an adjacent buffer slice on an output side. When data is read from an output buffer slice the FIFO buffer, all data in other buffer slices are shifted down one slice closer to the output side of the FIFO buffer.

Abstract: An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at that module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at that module, indicate to the other module that that module is ready to exit reset mode and exit the reset mode when the other module has also indicated that the other module is ready to exit reset mode.

Abstract: An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO buffer which includes a plurality of buffer slices including an output buffer slice wherein each of the plurality of buffer slices comprise a data register and a control bit register. A buffer slice is identified which is indicated for storing a data element based on a control bit register for the buffer slice and a control bit register of an adjacent buffer slice on an output side. When data is read from an output buffer slice the FIFO buffer, all data in other buffer slices are shifted down one slice closer to the output side of the FIFO buffer.