Abstract: An isolator provides bidirectional data transfer for a plurality of communications channels. First and second dies are located on first and second sides of a voltage isolation barrier and have a first and second plurality of digital data input/output pins associated therewith. First circuitry on the first die and third circuitry on the second die serializes a plurality of parallel digital data inputs from the digital data input/output pins onto one link across the barrier and transmits synchronization clock signals associated with the digital data inputs over a link across the barrier. Second circuitry on the second die and fourth circuitry on the first die de-serializes the digital data inputs from the first link onto the second digital data input/output pins and receives the first synchronization clock signal associated with the digital data inputs on the second link.

Abstract: A system for providing multiple communication channels over a single voltage isolation link includes first circuitry for multiplexing a plurality of digital data inputs from a plurality of communication channels onto the single voltage isolation link. Second circuitry de-multiplexes the plurality of digital data inputs from the single voltage isolation link to the plurality of communication channels. An RF isolator is used for providing the single voltage isolation link.

Abstract: An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry.

Abstract: An integrated circuit single chip isolator provides bidirectional data transfer for a plurality of communications channels. A first and second dies are located on a first and second sides of a voltage isolation barrier in the chip and have a first and second plurality of digital data input/output pins associated therewith. First circuitry located on the first die on a first side of the voltage isolation barrier and third circuitry located on the second die on a second side of the voltage isolation barrier serializes a plurality of parallel digital data inputs from the associated plurality of digital data input/output pins onto a one link across the voltage isolation barrier and transmits synchronization clock signals associated with the plurality of digital data inputs over a another link across the voltage isolation barrier.

Abstract: A system for providing multiple communication channels over a single voltage isolation link includes first circuitry for multiplexing a plurality of digital data inputs from a plurality of communication channels onto the single voltage isolation link. Second circuitry de-multiplexes the plurality of digital data inputs from the single voltage isolation link to the plurality of communication channels. An RF isolator is used for providing the single voltage isolation link.

Abstract: An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry.

Abstract: A multiple mode battery power supply contains first and second batteries, an external adapter port and a load port. The batteries are selectively connected to a node by way of associated power MOSFET switches. A power bus between the adapter port and the load port contains a MOSFET power switch. Finally a MOSFET power switch couples the node to the power bus. A controller selectively operates the power MOSFETS, to enable the load port to be powered by a selected one of any of an external adapter source of power, and one of the two batteries, while providing cross-conduction isolation among the external adapter source of power, and the batteries.