Abstract: Systems and methods can determine respiratory rates of a patient using a respiratory device by performing one or more frequency analyses of a signal from the gases flow. The signal from the gases flow can be one that varies with the patient's breathing. The system can include a non-sealed patient interface, such as a nasal cannula in a nasal high flow therapy, or any other patient interfaces. The respiratory system can also detect whether the patient has taken off the patient interface and/or whether the patient connected to the patient interface is talking or eating. Data of the patient's use of the respiratory system and the patient's respiratory rates can provide therapy compliance and long-term trend of use information and/or progress in the patient's respiratory functions and/or other physiological functions.

Abstract: Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.

Abstract: A field programmable gate array (FPGA) has non-highway wire segments for connection to logic blocks, and highway wire segments in a highway network of highways. Each highway has sets of highway wire segments in successive connection. Each successive connection is through a multiplexer. Multiplexers of highways have on-ramps, off-ramps, or both, for programmable connection to wire segments in accordance with programming the FPGA.

Abstract: Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.

Abstract: Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.

Abstract: Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.

Abstract: A field programmable gate array (FPGA) has non-highway wire segments for connection to logic blocks, and highway wire segments in a highway network of highways. Each highway has sets of highway wire segments in successive connection. Each successive connection is through a multiplexer. Multiplexers of highways have on-ramps, off-ramps, or both, for programmable connection to wire segments in accordance with programming the FPGA.