Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: Disclosed are multi-chip modules (MCMs) that allow for chip-to-chip transmission of light signals. The MCMs can incorporate at least two components, which are attached (e.g., by interconnects). For example, in one MCM disclosed herein, the two components can be an integrated circuit chip and an interposer to which the integrated circuit chip and one or more additional integrated circuit chips are attached by interconnects. In another MCM disclosed herein, the two components can be two integrated circuit chips that are stacked and attached to each other by interconnects. In either case, the two components can each have a waveguide and a grating coupler coupled to one end of the waveguide. The grating couplers on the different components can be approximately vertically aligned, thereby allowing light signals to be transmitted between the waveguides on those different components. Also, disclosed herein are methods of forming such MCMs.