Abstract: A system and method are disclosed for provisioning IP features in a system-on-chip. A plurality of identical chips are fabricated, each of which is capable of have a number of features enabled or disabled. As a default, all features are disabled. A production process is later carried out, in which the chip is installed in a greater device. During this process, the manufacturer requests a license the IP owner for enablement of various features. Using secure communications, a license is granted identifying the features to be enabled, and a volume of units permitted to be manufactured. The license information is encrypted using a key already known to the chip, and sent to the manufacturer. The chip receives the license information during provisioning, extracts relevant provisioning information using the key, and a secure processing system provisions the relevant features. Log information is generated to allow the IP owner to verify license compliance.

Abstract: A system and method are disclosed for provisioning IP features in a system-on-chip. A plurality of identical chips are fabricated, each of which is capable of have a number of features enabled or disabled. As a default, all features are disabled. A production process is later carried out, in which the chip is installed in a greater device. During this process, the manufacturer requests a license the IP owner for enablement of various features. Using secure communications, a license is granted identifying the features to be enabled, and a volume of units permitted to be manufactured. The license information is encrypted using a key already known to the chip, and sent to the manufacturer. The chip receives the license information during provisioning, extracts relevant provisioning information using the key, and a secure processing system provisions the relevant features. Log information is generated to allow the IP owner to verify license compliance.

Abstract: A system for multimedia content recognition includes a cloud server and a media client including a silicon-on-chip (SoC) device to communicate with the cloud server via a network. The SoC device includes a local area network (LAN) interface to receive media content from a media source and a media monitor to analyze the received media content and to generate signature information for transmission to the cloud server or for a local analysis. The SoC device further includes an inference engine to locally analyze the signature information to detect an unauthorized access.

Abstract: A system and method are disclosed for provisioning IP features in a system-on-chip. A plurality of identical chips are fabricated, each of which is capable of have a number of features enabled or disabled. As a default, all features are disabled. A production process is later carried out, in which the chip is installed in a greater device. During this process, the manufacturer requests a license the IP owner for enablement of various features. Using secure communications, a license is granted identifying the features to be enabled, and a volume of units permitted to be manufactured. The license information is encrypted using a key already known to the chip, and sent to the manufacturer. The chip receives the license information during provisioning, extracts relevant provisioning information using the key, and a secure processing system provisions the relevant features. Log information is generated to allow the IP owner to verify license compliance.

Abstract: Various systems and methods are provided for transmission of related data components across independent streams. In one embodiment, among others, a transmitting device may separate transmission data into related data components and transmit each related data component in an associated transport stream. Each related data component includes a synchronization tag associated with synchronization of the related data component within the transmission data. In another embodiment, a receiving device may receive related data components transmitted in separate transport streams and decode the related data components based at least in part upon a synchronization tag included in each related data component.

Abstract: Various systems and methods are provided for transmission of related data components across independent streams. In one embodiment, among others, a transmitting device may separate transmission data into related data components and transmit each related data component in an associated transport stream. Each related data component includes a synchronization tag associated with synchronization of the related data component within the transmission data. In another embodiment, a receiving device may receive related data components transmitted in separate transport streams and decode the related data components based at least in part upon a synchronization tag included in each related data component.

Abstract: Various systems and methods are provided for transmission of related data components across independent streams. In one embodiment, among others, a transmitting device may separate transmission data into related data components and transmit each related data component in an associated transport stream. Each related data component includes a synchronization tag associated with synchronization of the related data component within the transmission data. In another embodiment, a receiving device may receive related data components transmitted in separate transport streams and decode the related data components based at least in part upon a synchronization tag included in each related data component.

Abstract: Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

Abstract: Various systems and methods are provided for transmission of related data components across independent streams. In one embodiment, among others, a transmitting device may separate transmission data into related data components and transmit each related data component in an associated transport stream. Each related data component includes a synchronization tag associated with synchronization of the related data component within the transmission data. In another embodiment, a receiving device may receive related data components transmitted in separate transport streams and decode the related data components based at least in part upon a synchronization tag included in each related data component.

Abstract: A method includes determining a cache width of a cache of a processing device and determining a block size of image data processed by the processing device. The method further includes prefetching a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size. A processing system includes a memory component, a cache and an execution pipeline coupled to the memory component and the cache. The execution pipeline is to determine a cache width of the cache, determine a block size of image data stored at the memory component, and prefetch a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size.

Abstract: Whether a temperature of a portion of a die of an integrated circuit device having a central processing device and one or more peripheral components has exceeded a first temperature threshold is determined. In response to determining that the temperature of the portion of the die has exceeded the first temperature threshold, a first thermal reduction process for a first peripheral component of the one or more peripheral components is selected and the first thermal reduction process for the first peripheral component is implemented.

Abstract: A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller and dispatching a second memory access request to the memory controller in response to an anticipated completion of a memory access operation represented by the first memory access request. Another method includes receiving a first memory access request at a bus interface unit at a first time, dispatching a second memory access request to a memory controller at a second time subsequent to the first time, receiving a third memory access request at the bus interface unit at a third time subsequent to the second time, dispatching the third memory access request to the memory controller at a fourth time subsequent to the third time and dispatching the first memory access request to the memory controller at a fifth time subsequent to the fourth time.

Abstract: A method includes logically organizing rasterized image data into a first matrix of pixel tiles and individually rotating each pixel tile so as to generate a corresponding pixel tile of a second matrix representing an orthogonal representation of the first matrix. Each pixel tile represents a set of buffer lines of a frame buffer storing rasterized image data. The pixel tile is rotated by accessing and storing each buffer line of pixel data in a set of tile buffers such that the pixel data for each pixel in the same column position of an adjacent row is stored in a different tile buffer so that the set of tile buffers can be individually accessed to obtain pixel data for a set of pixels in the same column position in adjacent rows. This obtained pixel data is written to a second frame buffer as a row of pixel data for the corresponding pixel tile of the second matrix.

Abstract: A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan chain in response to a first value at a first bond pad. The first scan chain is bypassed to receive the first scan data at the second scan chain in response to a second value at the first bond pad.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller and dispatching a second memory access request to the memory controller in response to an anticipated completion of a memory access operation represented by the first memory access request. Another method includes receiving a first memory access request at a bus interface unit at a first time, dispatching a second memory access request to a memory controller at a second time subsequent to the first time, receiving a third memory access request at the bus interface unit at a third time subsequent to the second time, dispatching the third memory access request to the memory controller at a fourth time subsequent to the third time and dispatching the first memory access request to the memory controller at a fifth time subsequent to the fourth time.

Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

Abstract: A processing system comprising: i) a processor core; ii) a memory; iii) a plurality of peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the peripheral devices for transferring bus transactions between the processor core, the memory, and the peripheral devices. The communication bus comprises a bus controller for receiving memory access request data associated with a first memory access to a first location in the memory by a first one of the peripheral devices and transferring the received memory access request data to at least one memory address pin used to access the memory.