Patents by Inventor Brett W. Gaines

Brett W. Gaines has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Allocating cache lines
    Patent number: 7197605
    Abstract: Allocating cache lines includes incurring a cache write miss and, after incurring the cache write miss, writing data having a memory address to a cache line that does not include data at the memory address and that includes only invalid data.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 27, 2007
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Brett W. Gaines
  • Allocating cache lines
    Publication number: 20040128452
    Abstract: Allocating cache lines includes incurring a cache write miss and, after incurring the cache write miss, writing data having a memory address to a cache line that does not include data at the memory address and that includes only invalid data.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Mark A. Schmisseur, Brett W. Gaines