Abstract: There is described a map memory system with a time-multiplexed memory address bus wherein the mapping function is performed on the high order address bits in parallel with the output of the low order address bits on the time multiplex bus.

Abstract: There is provided an error detection and correction circuit which is optimized in terms of the operation, part count and the like. This invention includes parity generator circuitry to generate parity signals in accordance with a variation of the Hamming Code in response to the application of a plurality of input data bits. The parity signals are applied to a memory bus during a write cycle. During a read cycle, the parity generators produce a parity error signal, if appropriate, to indicate an error in parity. The error correction circuit receives the data bits from the memory (or memory bus) along with the parity error signals generated by the parity generator circuit portion. The data signals and parity error signals are gated together and supplied to Exclusive-OR gates. If an error is indicated by the level of the input signal, the Exclusive-OR gate converts the signal thereby correcting the erroneous data bit.