Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements includes a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up-table memory and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.

Abstract: A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.

Abstract: A logical circuit for maintaining uniform the density of the trace made on a photographic negative by the beam of a CR tube where the beam is subject to displacements in X and Y coordinate directions. The circuit includes a first bistable stage which represents by its state which (X or Y) displacement occurred last, and so controls (by way of a gating network and a second bistable stage) the beam intensity as to briefly reduce it whenever X and Y displacements occur alternately.