Abstract: A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.

Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.

Abstract: A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.

Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.

Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.

Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.

Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.

Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.

Abstract: A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.

Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.

Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.

Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.

Abstract: A probe for scanned probe microscopy is provided. The probe includes a cantilever beam and a tip. The cantilever beam extends along a generally horizontal axis. The cantilever beam has a crystal facet surface that is oriented at a tilt angle with respect to the generally horizontal axis. The tip projects outwardly from the crystal facet surface.

Abstract: A probe for scanned probe microscopy is provided. The probe includes a cantilever beam and a tip. The cantilever beam extends along a generally horizontal axis. The cantilever beam has a crystal facet surface that is oriented at a tilt angle with respect to the generally horizontal axis. The tip projects outwardly from the crystal facet surface.

Abstract: A method of creating a probe for scanned probe microscopy is disclosed. The method includes providing a wafer having a support wafer layer and a device layer. The method includes masking the wafer with a masking layer. The method includes removing a portion of the masking layer at the device layer. The method includes etching the wafer along the portion of the masking layer that has been removed to create a crystal facet surface that is oriented at a tilt angle. The method includes epitaxially growing a tip along the crystal facet surface.

Abstract: An electrical connector system includes first and second electrical connectors mateable in a given general direction (A). Each connector includes a housing having a mating end and at least a pair of terminals mounted on the housing. The pair of terminals of each connector have contact portions engageable with the contact portions of the pair of terminals of the other connector. The contact portions of the terminals of at least one of the connectors are at angles to the mating direction to define a generally V-shaped engaging configuration. The contact portions of the terminals of at least one of the connectors are resilient. Therefore, wiping engagement between the respective terminals is effected during mating of the connectors, and the resilient contact portions are effective to store energy upon mating of the connectors, which energy is effective to assist in unmating of the connectors.

Abstract: An electrical connector assembly is disclosed for connecting a mating connector to a printed circuit board. The assembly includes a dielectric housing having a plurality of terminal-receiving cavities and a plurality of terminals insertable into the cavities. Each terminal includes a base section insertable into a respective cavity in an insertion direction for securing the terminal in the cavity. The terminal includes a tail section for contacting the printed circuit board and spring contact beam for electrically engaging a conductor of the mating connector. The tail section and the spring contact beam extend from the base section and are spaced apart transverse to the insertion direction, whereby an insertion tool can be inserted therebetween into engagement with the base section to readily force the terminal into its terminal-receiving cavity.