Patents by Inventor Brian A. Buchner

Brian A. Buchner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105125
    Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 11, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd E. Martin, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
  • Publication number: 20140152675
    Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Todd E. MARTIN, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
  • Patent number: 8502832
    Abstract: Apparatus and systems utilizing fixed point filtering to perform floating point texture filtering. A texture pipe unit consisting of a texture addressing unit, texture cache unit, and texture filter unit accepts texture requests for a specified pixel from a resource and returns formatted bilinear filtered results based on the specific pixel's corresponding four texels. The texture filtering unit consists of a pre-formatter module, interpolator module, accumulator module and a format module. The pre-formatter module accepts texel data in a floating point or fixed point format. However, if the data is in a floating point format the pre-formatter module converts the floating point data into a normalized fixed point data format whereby the interpolator module may perform its bilinear interpolator functions using standardized fixed point systems and apparatus without necessitating the use of floating point arithmetic units.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 6, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian A. Buchner, Anthony P. DeLaurier
  • Patent number: 8482559
    Abstract: Tessellation triangles, which are used to model three-dimensional surfaces in computer-generated graphics, can be more efficiently calculated by retrieving tessellation triangle vertices and Bezier-function coefficients using a single, two-part address.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: July 9, 2013
    Assignee: ATI Technologies ULC
    Inventors: Brian A. Buchner, Vineet Goel
  • Publication number: 20090300293
    Abstract: Methods and systems for dynamically partitioning a cache and maintaining cache coherency are provided. In an embodiment, a system for processing memory requests includes a cache and a cache controller configured to compare a memory address and a type of a received memory request to a memory address and a type, respectively, corresponding to a cache line of the cache to determine whether the memory request hits on the cache line. In another embodiment, a method for processing fetch memory requests includes receiving a memory request and determining if the memory request hits on a cache line of a cache by determining if a memory address and a type of the memory request match a memory address and a type, respectively, corresponding to a cache line of the cache.
    Type: Application
    Filed: July 1, 2008
    Publication date: December 3, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael J. MANTOR, Brian A. Buchner, John P. McCardle, II
  • Patent number: 7594069
    Abstract: An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: September 22, 2009
    Assignee: ATI Technologies, Inc.
    Inventors: Jeffrey T. Brady, Brian A. Buchner, Rex E. McCrary, Ralph C. Taylor
  • Publication number: 20040085312
    Abstract: Tessellation triangles, which are used to model three-dimensional surfaces in computer-generated graphics, can be more efficiently calculated by retrieving tessellation triangle vertices and Bezier-function coefficients using a single, two-part address.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Inventors: Brian A. Buchner, Vineet Goel