Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.

Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; and a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM.

Abstract: A system for generating analog output from a field programmable gate array. The field programmable gate array has a plurality of digital transceivers, each including a transmitter with an output drive circuit having a programmable output voltage swing. Two or more of the transmitters are programmed to have output voltage swings differing from each other by about a factor of two. A circuit that operates as a digital to analog converter is formed by combining the outputs of the transmitters, using a power combiner.

Abstract: Embodiments of a phase difference estimator and method are generally described herein. The phase difference estimator includes a delay element to delay a reference clock signal that includes an alternating symbol waveform by one of a plurality of delay values. The phase difference estimator further includes a sampler to sample a monitored clock signal provided by a second device responsive to edges of the delayed reference clock signal to generate a sampled signal output. The phase difference estimator further includes a correlation element to correlate the sampled signal output of the sampler with a step function to generate a correlation value for each delay value, and a controller to instruct the delay element to delay the reference clock signal by one of the delay values and provide a phase difference estimate output indicative of a phase difference between the reference and monitored clock signals based on the correlation value.

Abstract: A system for generating analog output from a field programmable gate array. The field programmable gate array has a plurality of digital transceivers, each including a transmitter with an output drive circuit having a programmable output voltage swing. Two or more of the transmitters are programmed to have output voltage swings differing from each other by about a factor of two. A circuit that operates as a digital to analog converter is formed by combining the outputs of the transmitters, using a power combiner.

Abstract: A system for generating analog output from a field programmable gate array. The field programmable gate array has a plurality of digital transceivers, each including a transmitter with an output drive circuit having a programmable output voltage swing. Two or more of the transmitters are programmed to have output voltage swings differing from each other by about a factor of two. A circuit that operates as a digital to analog converter is formed by combining the outputs of the transmitters, using a power combiner.

Abstract: Embodiments of a phase difference estimator and method are generally described herein. The phase difference estimator includes a delay element to delay a reference clock signal that includes an alternating symbol waveform by one of a plurality of delay values. The phase difference estimator further includes a sampler to sample a monitored clock signal provided by a second device responsive to edges of the delayed reference clock signal to generate a sampled signal output. The phase difference estimator further includes a correlation element to correlate the sampled signal output of the sampler with a step function to generate a correlation value for each delay value, and a controller to instruct the delay element to delay the reference clock signal by one of the delay values and provide a phase difference estimate output indicative of a phase difference between the reference and monitored clock signals based on the correlation value.

Abstract: A Decision Feedback Equalizer (DFE) is used as the predictive filter in a Sigma-Delta feedback loop as part of a Sigma-Delta Analog-to-Digital Converter. The tap weights of the DFE are chosen to provide adaptive noise shaping for receiving signals of various frequencies multiplexed in time.

Abstract: A link-path delay estimator estimates a signal-path delay of a signal path between a master device and a remote device, by combining coarse delay estimates and a fine delay estimate. The coarse delay estimates indicate only an integral portion of the signal-path delay, selected as an integral multiple of a symbol period. The fine delay estimate indicates only a fractional portion of the signal-path delay, selected from a range of values that extends over one symbol period. The link-path delay estimator can combine the coarse and fine delay estimates using a first rule if the two most recent coarse delay estimates are equal, and a second rule if the two most recent coarse delay estimates differ. The coarse delay estimates can arise from both rising edges and falling edges of periodic signals sent along the signal path.

Abstract: Embodiments of a high-resolution link-path delay estimator and method are generally described herein. The high-resolution link-path delay estimator may estimate a signal-path delay of a signal path between a master and remote device. The high-resolution link-path delay estimator may phase-shift a transmit signal of alternating symbols by phase-shift values and may sample a loopback signal. A noise-reduced version of the sampled signal output may be correlated with a step function to generate a correlation value for each of the phase-shift values. One of the phase-shift values may be selected to generate a fine-delay estimate which may be added to a coarse delay estimate to determine the signal-path delay. The coarse delay estimate may be an estimate of the signal-path delay to a nearest symbol period of the transmit signal and the fine-delay estimate may be an estimate to within a fraction of the symbol period.

Abstract: A link-path delay estimator estimates a signal-path delay of a signal path between a master device and a remote device, by combining coarse delay estimates and a fine delay estimate. The coarse delay estimates indicate only an integral portion of the signal-path delay, selected as an integral multiple of a symbol period. The fine delay estimate indicates only a fractional portion of the signal-path delay, selected from a range of values that extends over one symbol period. The link-path delay estimator can combine the coarse and fine delay estimates using a first rule if the two most recent coarse delay estimates are equal, and a second rule if the two most recent coarse delay estimates differ. The coarse delay estimates can arise from both rising edges and falling edges of periodic signals sent along the signal path.

Abstract: A method for tuning used in a broadcast data system having a receiving station with a memory, wherein the receiver station files data and real-time data is disclosed. The method includes storing the memory in a table having tuning information corresponding to a plurality of IP addresses and ports, receiving a download request based on a user input, and using the download request to identify download information including an IP address and a port. The method further includes using the identified IP address and port to open a connection to a socket, using the table to determine tuning information corresponding to the identified IP address and port, and using the tuning information to tune the receiver station to the identified IP address and port.