Patents by Inventor Brian A. Kaiser

Brian A. Kaiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6278185
    Abstract: A substrate which has a first conductive layer that is attached to a first dielectric layer. A second conductive layer is attached to the first dielectric layer. The second conductive layer may be a plated copper material that extends through a via opening of the dielectric and is attached to the first conductive layer. A third conductive layer is attached to the second conductive layer, including a sidewall of the third layer. A second dielectric can be attached to the third conductive layer. The third conductive layer may be a plated nickel-copper composition which improves the adhesion to subsequent layers in the substrate, particularly between the second dielectric and the sidewall of the second conductive layer.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: August 21, 2001
    Assignee: Intel Corporation
    Inventors: Venkatesan Murali, Kenzo Ishida, Brian A. Kaiser, Anant Vaidyanathan
  • Patent number: 6248951
    Abstract: An integrated circuit package which may include a decal that is attached to a substrate which supports an integrated circuit. The decal may have a coefficient of thermal expansion that is different than a coefficient of thermal expansion of the substrate.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: June 19, 2001
    Assignee: Intel Corporation
    Inventors: Venkatesan Murali, Nagesh Vodrahalli, Brian A. Kaiser
  • Patent number: 5139971
    Abstract: A method of forming a device having an intermetal dielectric film which is formed and annealed to prevent a significant quantity of ambient moisture from being absorbed by the intermetal dielectric film prior to passivation layer deposition is disclosed. An intermetal dielectric layer is formed over a substrate having a interconnection layer. A second interconnect layer is formed over the IMD layer. The substrate with the intermetal dielectric is annealed anytime between IMD formation and passivation layer deposition to produce a film that does not absorb a significant quantity of ambient moisture, and therefore, longer queue times can be utilized between the anneal and subsequent processing. The present invention reduces the amount of water in the device which reduces hot electron induced device degradation.
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: August 18, 1992
    Assignee: Intel Corporation
    Inventors: Ragupathy V. Giridhar, Philip E. Freiberger, Brian A. Kaiser, Yi-Ching Lin