Abstract: The phase detector of a phase-lock loop comprises a double balanced mixer that compares the phase of the output signal of the loop oscillator with that of a reference signal and combines the resultant error control voltage with a constant sweep voltage that is stepped at a variable rate. When the loop is out of lock, a counter circuit increments the contents thereof for every n excursions of the difference frequency signal from the phase detector that exceed a prescribed threshold level. A D-A converter converts each unique count to a corresponding constant amplitude step of the stepped sweep voltage. Since the difference between the frequencies of the oscillator and reference signals decreases as the loop approaches lock, the rates at which the counter is incremented and the sweep voltage changes value also decrease. Thus, the loop is swept at a slower rate as the frequencies of the reference and oscillator signals converge.

Abstract: In satellite telephone communication equipment, the phase detector of a phase-lock loop compares the phase of a master oscillator signal from the loop oscillator with that of a pilot tone signal and produces an error control voltage which it combines with a constant sweep voltage that is stepped at a variable rate. When the loop is out of lock, a first count of the number of excursions of the beat or difference frequency signal from the phase detector that exceed a prescribed threshold level is generated, a second count is incremented for every n counts in the first count, and a constant amplitude step of the stepped sweep voltage is produced for each unique value of the second count. The steps in the sweep voltage occur at a variable rate that is related to the difference frequency of the beat signal. Since the difference between the oscillator and pilot frequencies decreases as the loop approaches lock, the rate at which the sweep voltage is stepped also decreases.