Abstract: According to one general aspect, a method may include receiving at least a portion of a packet of data by an ingress device. The method may include determining an egress device to receive the packet. In some embodiments, the method may include dividing the received portion of the packet into a plurality of segments. The method may include editing, for each segment, a header to include an address field that indicates the address of the egress device, wherein the header is associated with a current segment. The method may include, for each segment, editing the header to include a next link field that indicates a link that will be used to transmit the next segment of the packet. The method may also include transmitting the current segment and header to the egress device via the link indicated in the next link field of the header of a preceding segment.

Abstract: Methods and apparatus for processing packet data are disclosed. An example apparatus includes a plurality of network interfaces configured to send and receive packet data. The example apparatus further includes a switching module coupled with the plurality of network interfaces, the switching module being configured to communicate the packet data to and from the plurality of network interfaces. The example apparatus still further includes a fabric interface controller coupled with the switching module. The example apparatus also includes a virtual fabric interface controller coupled with the fabric interface controller.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results.

Abstract: According to one general aspect, an apparatus may include an ingress port, a header cache, and a plurality of ingress recursion engines. In some embodiments, the ingress port may be configured to receive a packet that comprises a data portion and a header portion, wherein the header portion comprises at least one header. In various embodiments, the header cache may be configured to store at least a part of the header portion of the packet. In one embodiment, the plurality of ingress recursion engines may be configured to recursively process the header portion, from outer-most header to inner-most header, until an adjacency value for the packet is determined. In some embodiments, each ingress recursion engine may be configured to process a header from the header portion.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.

Abstract: An architecture for a multi-port switching device is described having a very regular structure that lends itself to scaling for performance speed and a high level of integration. The distribution of packet data internal to the chip is described as using a cell-based TDM packet transport configuration such as a ring. Similarly, a method of memory allocation in a transmit buffer of each port allows for reassembly of the cells of a packet for storage in a contiguous manner in a queue. Each port includes multiple queues. The destination queue and port for a packet is identified in a multi-bit destination map that is prepended to the start cell of the packet and used by a port to identify packets destined for it. The architecture is useful for a single-chip multi-port Ethernet switch where each of the ports is capable of 10 Gbps data rates.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: A general purpose, software-controlled central processor (CP) can be augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, a packet deconstructor, a search engine, and a packet editor. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability.

Abstract: Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.

Abstract: Methods and apparatus for enabling communication between a source network device and one or more destination network devices are disclosed. The source network device and the one or more destination network devices are connected via an associated interconnect to a switch having a memory associated therewith. One or more messages are composed at the source network device, where the messages include data and control information associated with the data. The messages are then sent to the switch to enable the data and at least a portion of the control information to be stored in the memory associated with the switch, where the data is stored for retrieval by the one or more destination network devices.

Abstract: Methods and apparatus for providing a source interface device and destination interface device are disclosed. A method of enabling communication between the source device and one or more destination devices includes sending data from the source device to the switch for storage. A frame notify message addressed to the one or more destination devices and indicating that the data has been stored by the switch for retrieval is then sent on the ring interconnect. One of the specified destination devices obtains the frame notify message from the source device via the ring interconnect. A frame retrieval message identifying the data is then sent from the destination device to the switch in response to the frame notify message. In addition, the destination device modifies the frame notify message to indicate whether the destination device was capable of accepting the frame notify message.

Abstract: Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.

Abstract: Methods and apparatus for enabling communication between a source network device and one or more destination network devices are disclosed. A system enabling communication between a source network device and one or more destination network devices includes a switch and a ring interconnect. The switch is adapted for connecting to the source network device and the one or more destination network devices. More particularly, the switch is capable of storing data provided by the source network device and retrieving the data for the one or more destination network devices. The ring interconnect is adapted for connecting the source network device and the one or more destination network devices to one another. In addition, the ring interconnect is capable of passing one or more free slot symbols along the ring interconnect.

Abstract: A computer bus adapter device which is coupled to a true parallel computer bus is automatically set to a pre-determined configuration in response to configuration data provided to the bus by a host process. During a set-up portion of an initialization procedure, the adapter device recognizes a data sequence and uses information based on the recognized data sequence to configure itself to respond to its host process. In a specific embodiment, the desired configuration information is stored in non-volatile storage associated with the host process, such as a magnetic file or a non-volatile random access memory.