Abstract: There is provided a method for fabricating a vertically tapered spot-size converter on a substrate, comprising: growing a waveguide core on the substrate; coating the waveguide core with a photoresist layer; placing a photomask having patterns at a negative focus offset point with respect to the photoresist layer, the patterns being defined by openings in the photomask, each opening having a cross-section comprising a region of constant width and at least one region of non-constant width, the non-constant width reducing in a direction extending away from the region of constant width; transferring the patterns of the photomask to the photoresist layer; providing the waveguide core with a vertically tapered profile, the vertically tapered profile being provided by the patterns of the photomask; growing a cladding layer over the waveguide core; and patterning and etching the cladding layer and the waveguide core, thereby defining the vertically tapered spot-size converter.

Abstract: The present invention relates to a sol-gel deposition/heat treatment process, which consistently produces polycrystalline direct bandgap semiconductor, e.g. ZnO, thin films exhibiting a photo luminescent (PL) spectrum at room temperature that is dominated by a single peak, e.g. in the ultraviolet part of the spectrum, in which the PL intensity of the bandgap emission is more than approximately 40 times greater than any deep-level defect emission peak or band. The present invention incorporates such direct bandgap semiconductor, e.g. ZnO, polycrystalline thin films produced by the method of the present invention into electro-luminescent devices that exhibit similarly high ratios of bandgap/deep-level defect emission intensity.

Abstract: A method of forming a semiconductor structure, and a structure thereof are provided. The method is based on a novel lift-off masking process, and has particular application for forming gate structures for FETs with sputtered metals. After providing a weakly bonded surface layer on the substrate, a multilayer masking layer stack is deposited, and patterned to define an opening with undercut sidewalls. The multilayer masking stack forms a heat resistant mask for nigh temperature deposition of one or more conductive layers, e.g. sputtered metals to form a gate metal stack for a FET. The undercut sidewalls of the mask create a discontinuity in the deposited metal layers. Preferential etching of the deposited metal layers occurs at the discontinuity, resulting in separation of the gate metal structure and the excess metal overlying the masking layers.

Abstract: A high temperature furnace including a furnace chamber maintained at an internal temperature above the ignition temperature of a gas mixture used for the growth of oxide layers on silicon substrates therein. A separate burn chamber is used to mix and burn the gas mixture. A tube conveys the mixture into the furnace chamber so that ignition of the gas mixture in the furnace chamber creates a flame front that travels back along the tube to the burn chamber to sustain ignition therein.