Abstract: A drive and control system is provided for a towing vehicle pulling a towed implement, such as a tractor pulling a scraper. The drive system includes a diesel engine which drives a generator for generating electric power. A tractor axle drive motor is connected to driven wheels of the tractor through a transmission. An assist drive motor is drivingly connected to driven wheels of the scraper. A power distribution unit controls distribution of electric power from the generator to the tractor and implement assist drive motors. A control unit controls the power distribution unit as a function of an operator set power split, and other sensed parameters. A one-way clutch prevents over-speed of the assist drive motor.

Abstract: A drive and control system is provided for a towing vehicle pulling a towed implement, such as a tractor pulling a scraper. The drive system includes a diesel engine which drives a generator for generating electric power. A tractor axle drive motor is connected to driven wheels of the tractor through a transmission. An assist drive motor is drivingly connected to driven wheels of the scraper. A power distribution unit controls distribution of electric power from the generator to the tractor and implement assist drive motors. A control unit controls the power distribution unit as a function of an operator set power split, and other sensed parameters. A one-way clutch prevents over-speed of the assist drive motor.

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.