Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states.

Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

Abstract: A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.