Abstract: A method and device are disclosed for providing an ultra low-noise hand gap voltage reference. The method detects a first voltage drop across a first diode reference, and a second voltage drop across a second voltage reference that includes a second diode. The first and second voltage drops are compared. Temperature compensation currents are supplied to the first diode reference and second voltage references in addition to constant currents, where the constant currents have the same value across a first temperature range. As a result of the constant current, a minimal amount of temperature compensation current is required. Alternatively stated, temperature compensation current is provided having a rate of change greater than PTAT. In response to comparing the first voltage drop to the second voltage drop, a true sub-volt hand gap voltage is supplied across a third voltage reference including a diode, that is constant across the first temperature range.

Abstract: Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Abstract: An integrated voltage controlled oscillator (VCO) circuit which utilizes the relative capacitance ratio between capacitors and the relative resistance ratio between resistors in an integrated circuit (IC) to output a signal having a predictable frequency for a given control signal voltage. The VCO output frequency will not vary more than 3.0% from one IC chip implementing the VCO circuit, to the next. This low variance between IC chips is derived from the phenomenon whereby the respective ratios of capacitance and resistance between capacitors and resistors in the IC will not vary more than .+-.1.5% from the ratios of like capacitors and resistors on other IC chips. The integrated VCO circuit includes a control signal subcircuit, integrator subcircuit, filter subcircuit, and comparator unit subcircuit.

Abstract: A driving grid is driven by an ac signal comprising a carrier frequency modulated by a lower frequency. An untethered, batteryless pointer includes a pick-up coil in a first tuned circuit tuned to the carrier frequency, connected by diodes to a driving coil in a second tuned circuit tuned to the lower modulating frequency. Energy picked up by the first tuned circuit from the driving grid at the carrier frequency drives the second tuned circuit at the modulating frequency. Modulating frequency signals induced in the receiving grid conductors are used to locate the pointer in the usual manner. Because the carrier signal contains no frequency component of the modulating signal, the driving grid and receiving grid are sufficiently decoupled.