Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.

Abstract: A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.

Abstract: A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.

Abstract: A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.

Abstract: A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.

Abstract: A programmable output interface in an Open System Interconnection (OSI) enables a Media Access (MAC) Layer to access a variety of Physical (PHY) Layer implementations without redesign of the interface. The programmable interface includes a control signal generator; an output clock gating generator, and an output polarity control device coupled to the PHY layer. The interface receives media access Start; media access Done signals; a Data Rate clock signal and a data signal. The control signal generator provides control signals for the physical layer components via the polarity control device. The active signal polarity and the relative timing of the control signals are controlled by programmable registers. The output clock gating generator provides clock signals to the physical layer components via the polarity control in response to the Start; Done and Data Rate signals.

Abstract: An asynchronous transmission mode data cell header includes virtual channel and virtual path identifiers which are resolved into logical channel identifiers at the user interface by two table lookup operations. The virtual path identifier is used to access a virtual path table entry having a variable length pointer value buffered out to a fixed length field by zeros with a binary one at the boundary position. Using the binary one as a marker, the pointer field is extracted and concatenated with a base register value and the lower order bits of the virtual channel identifier, corresponding to the bit position of the binary one marker, to provide an index into a logical channel identifier table. The logical channel identifier is used to associate the data cell attached to that header with the appropriate user data stream.