Patents by Inventor Brian Albert Lowe, Jr.

Brian Albert Lowe, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8294440
    Abstract: Multiple embodiments of a linear voltage regulator are described that use a bipolar output transistor to deliver current and a regulated voltage to a load. The bipolar output transistor assures low output impedance providing isolation from load induced noise. A first depletion mode field effect transistor FET drives the output transistor dependent on a correction signal from an error amplifier. The error amplifier compares a fixed voltage reference to a portion of the output voltage to set a control voltage for the FET gate. Output voltage is set with an offset voltage referenced to circuit ground and can be generated with a single resistor to circuit ground by a current through the resistor which is set from VREF and the regulated output voltage. Output current is limited with a second depletion mode FET that senses the difference in regulator output voltage and voltage at said first FET transistor drain.
    Type: Grant
    Filed: March 20, 2010
    Date of Patent: October 23, 2012
    Inventor: Brian Albert Lowe, Jr.
  • Publication number: 20100327834
    Abstract: Multiple embodiments of a linear voltage regulator are described that use a bipolar output transistor to deliver current and a regulated voltage to a load. The bipolar output transistor assures low output impedance providing isolation from load induced noise. A first depletion mode field effect transistor FET drives the output transistor dependent on a correction signal from an error amplifier. The error amplifier compares a fixed voltage reference to a portion of the output voltage to set a control voltage for the FET gate. Output voltage is set with an offset voltage referenced to circuit ground and can be generated with a single resistor to circuit ground by a current through the resistor which is set from VREF and the regulated output voltage. Output current is limited with a second depletion mode FET that senses the difference in regulator output voltage and voltage at said first FET transistor drain.
    Type: Application
    Filed: March 20, 2010
    Publication date: December 30, 2010
    Inventor: Brian Albert Lowe, JR.