Abstract: A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: Processing pixels in a graphics pipeline. Screen coincidence between a first pixel and a second pixel in a graphics pipeline is detected, wherein the first pixel has entered a downstream pipeline portion of the graphics pipeline but has not yet completed processing within the graphics pipeline. In response to detecting the coincidence, propagation of the second pixel to the downstream pipeline portion is stalled until the first pixel completes processing within the graphics pipeline. A data cache associated with the data fetch stage is invalidated in advance of a data fetch stage of the downstream pipeline portion obtaining data for the second pixel.

Abstract: A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator.

Abstract: A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier.

Abstract: A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.

Abstract: A graphics processor includes programmable arithmetic logic units (ALUs) for performing scalar arithmetic operations on pixel packets. For a selected scalar arithmetic operation, operands in pixel packets may be formatted in a S1.8 format to improve dynamic range. For at least one other scalar arithmetic operation, the pixel packets may be formatted in a different data format.

Abstract: A graphics processor has elements of a graphics pipeline coupled by distributors. The distributors permit the process flow of pixel packets through the pipeline to be reconfigured in response to a command from a host.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: A graphics processor includes an arithmetic logic unit (ALU) stage for processing pixel packets. Pixels are assigned as either even pixels or odd pixels. The pixel packets of odd and even pixels are interleaved to account for ALU latency.